diff mbox series

[v2,11/19] riscv: add ISA extension parsing for Zihintntl

Message ID	20231017131456.2053396-12-cleger@rivosinc.com
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) client-ip=23.128.96.35; From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com> To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com>, Palmer Dabbelt <palmer@rivosinc.com>, Paul Walmsley <paul.walmsley@sifive.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Albert Ou <aou@eecs.berkeley.edu>, Jonathan Corbet <corbet@lwn.net>, Andrew Jones <ajones@ventanamicro.com>, Evan Green <evan@rivosinc.com>, Conor Dooley <conor@kernel.org>, Samuel Ortiz <sameo@rivosinc.com> Subject: [PATCH v2 11/19] riscv: add ISA extension parsing for Zihintntl Date: Tue, 17 Oct 2023 15:14:48 +0200 Message-ID: <20231017131456.2053396-12-cleger@rivosinc.com> In-Reply-To: <20231017131456.2053396-1-cleger@rivosinc.com> References: <20231017131456.2053396-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	riscv: report more ISA extensions through hwprobe \| [v2,00/19] riscv: report more ISA extensions through hwprobe [v2,01/19] riscv: hwprobe: factorize hwprobe ISA extension reporting [v2,02/19] riscv: add ISA extension parsing for scalar crypto [v2,03/19] riscv: hwprobe: add support for scalar crypto ISA extensions [v2,04/19] dt-bindings: riscv: add scalar crypto ISA extensions description [v2,05/19] riscv: add ISA extension parsing for vector crypto extensions [v2,06/19] riscv: hwprobe: export vector crypto ISA extensions [v2,07/19] dt-bindings: riscv: add vector crypto ISA extensions description [v2,08/19] riscv: add ISA extension parsing for Zfh/Zfhmin [v2,09/19] riscv: hwprobe: export Zfh/Zfhmin ISA extensions [v2,10/19] dt-bindings: riscv: add Zfh[min] ISA extensions description [v2,11/19] riscv: add ISA extension parsing for Zihintntl [v2,12/19] riscv: hwprobe: export Zhintntl ISA extension [v2,13/19] dt-bindings: riscv: add Zihintntl ISA extension description [v2,14/19] riscv: add ISA extension parsing for Zvfh[min] [v2,15/19] riscv: hwprobe: export Zvfh[min] ISA extensions [v2,16/19] dt-bindings: riscv: add Zvfh[min] ISA extension description [v2,17/19] riscv: add ISA extension parsing for Zfa [v2,18/19] riscv: hwprobe: export Zfa ISA extension [v2,19/19] dt-bindings: riscv: add Zfa ISA extension description

Commit Message

Clément Léger Oct. 17, 2023, 1:14 p.m. UTC

  Add parsing for Zihintntl ISA extension[1] that was ratified in commit
0dc91f5 ("Zihintntl is ratified") of riscv-isa-manual[2].

Link: https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/view [1]
Link: https://github.com/riscv/riscv-isa-manual/commit/0dc91f505e6d [2]
Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 arch/riscv/include/asm/hwcap.h | 1 +
 arch/riscv/kernel/cpufeature.c | 1 +
 2 files changed, 2 insertions(+)

Comments

Evan Green Oct. 18, 2023, 5:28 p.m. UTC | #1

On Tue, Oct 17, 2023 at 6:15 AM Clément Léger <cleger@rivosinc.com> wrote:
>
> Add parsing for Zihintntl ISA extension[1] that was ratified in commit
> 0dc91f5 ("Zihintntl is ratified") of riscv-isa-manual[2].
>
> Link: https://drive.google.com/file/d/13_wsN8YmRfH8YWysFyTX-DjTkCnBd9hj/view [1]
> Link: https://github.com/riscv/riscv-isa-manual/commit/0dc91f505e6d [2]
> Signed-off-by: Clément Léger <cleger@rivosinc.com>

Reviewed-by: Evan Green <evan@rivosinc.com>

diff mbox series

Patch

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index bead05cb0df2..a9aea62b6c6f 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -81,6 +81,7 @@ 
 #define RISCV_ISA_EXT_ZVKT		63
 #define RISCV_ISA_EXT_ZFH		64
 #define RISCV_ISA_EXT_ZFHMIN		65
+#define RISCV_ISA_EXT_ZIHINTNTL		66
 
 #define RISCV_ISA_EXT_MAX		128
 
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 68914b5e2df9..0a74b2cdcacf 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -242,6 +242,7 @@  const struct riscv_isa_ext_data riscv_isa_ext[] = {
 	__RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR),
 	__RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR),
 	__RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI),
+	__RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL),
 	__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
 	__RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM),
 	__RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH),