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[2620:137:e000::3:6]) by mx.google.com with ESMTPS id y28-20020aa78f3c000000b006be55174f3fsi979163pfr.28.2023.10.16.23.47.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 23:47:58 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) client-ip=2620:137:e000::3:6; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=dTIQXiE4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id 65366802F8E0; Mon, 16 Oct 2023 23:47:55 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234422AbjJQGro (ORCPT + 19 others); Tue, 17 Oct 2023 02:47:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52310 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234543AbjJQGrf (ORCPT ); Tue, 17 Oct 2023 02:47:35 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 18655F1; Mon, 16 Oct 2023 23:47:32 -0700 (PDT) X-UUID: 04bf65206cb911eea33bb35ae8d461a2-20231017 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=BOknq7sF98YK+HRUp3woWcsMacelNgGfHkaunLKrevE=; b=dTIQXiE4H1g+OppcVHEkZ+BI2vBytNubzycAgJ47GDm5nyjBGroXSbUfO84f3Yt1P2CU9q+/CwRVpcr+Yw5xrh20c9LrIZ7xHj6OV7Ephc8OPdDqoGymPjXN7cExhu1/NymyrKKFhYfta2fP+eCc+itzcGw16+c4teuHztwz4u0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:eb2c0085-3415-44ae-a6d3-381ea8566e30,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:5f78ec9,CLOUDID:7deb36c4-1e57-4345-9d31-31ad9818b39f,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 04bf65206cb911eea33bb35ae8d461a2-20231017 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 709946702; Tue, 17 Oct 2023 14:47:19 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 17 Oct 2023 14:47:19 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 17 Oct 2023 14:47:18 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu , Krzysztof Kozlowski , Matthias Brugger CC: Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Chen-Yu Tsai , Sean Paul , , , , , , Singo Chang , Nancy Lin , Jason-JH Lin , Hsiao Chien Sung Subject: [PATCH v3 05/11] drm/mediatek: Set DRM mode configs accordingly Date: Tue, 17 Oct 2023 14:47:11 +0800 Message-ID: <20231017064717.21616-6-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231017064717.21616-1-shawn.sung@mediatek.com> References: <20231017064717.21616-1-shawn.sung@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Mon, 16 Oct 2023 23:47:55 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779984266143179266 X-GMAIL-MSGID: 1779984266143179266 Set DRM mode configs limitation accroding to the hardware capabilities. Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 28 ++++++++++++++++++-------- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 17 ++++++++++++++++ 2 files changed, 37 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 5d551bff6b3f..a4b740420ebb 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -304,6 +304,7 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = { .conn_routes = mt8188_mtk_ddp_main_routes, .conn_routes_num = ARRAY_SIZE(mt8188_mtk_ddp_main_routes), .mmsys_dev_num = 2, + .max_pitch = GENMASK(15, 0), }; static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { @@ -318,6 +319,7 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { .main_path = mt8195_mtk_ddp_main, .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main), .mmsys_dev_num = 2, + .max_pitch = GENMASK(15, 0), }; static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { @@ -325,6 +327,7 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = { .ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext), .mmsys_id = 1, .mmsys_dev_num = 2, + .max_pitch = GENMASK(15, 0), }; static const struct of_device_id mtk_drm_of_ids[] = { @@ -463,16 +466,16 @@ static int mtk_drm_kms_init(struct drm_device *drm) if (ret) goto put_mutex_dev; - drm->mode_config.min_width = 64; - drm->mode_config.min_height = 64; - /* - * set max width and height as default value(4096x4096). - * this value would be used to check framebuffer size limitation - * at drm_mode_addfb(). + * Set default values for drm mode config + * these values will be referenced by drm_mode_addfb() as + * frame buffer size limitation. */ - drm->mode_config.max_width = 4096; - drm->mode_config.max_height = 4096; + drm->mode_config.min_width = 1; + drm->mode_config.min_height = 1; + drm->mode_config.cursor_width = 512; + drm->mode_config.cursor_height = 512; + drm->mode_config.funcs = &mtk_drm_mode_config_funcs; drm->mode_config.helper_private = &mtk_drm_mode_config_helpers; @@ -502,6 +505,15 @@ static int mtk_drm_kms_init(struct drm_device *drm) for (j = 0; j < private->data->mmsys_dev_num; j++) { priv_n = private->all_drm_private[j]; + if (priv_n->data->max_pitch) { + /* Save 4 bytes for the color depth (pitch = width x bpp) */ + drm->mode_config.max_width = priv_n->data->max_pitch >> 2; + drm->mode_config.max_height = priv_n->data->max_pitch >> 2; + } else { + drm->mode_config.max_width = 4096; + drm->mode_config.max_height = 4096; + } + if (i == 0 && priv_n->data->main_len) { ret = mtk_drm_crtc_create(drm, priv_n->data->main_path, priv_n->data->main_len, j, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index d2efd715699f..833ecee855bb 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -28,6 +28,21 @@ struct mtk_drm_route { const unsigned int *route_ddp; }; +/** + * struct mtk_mmsys_driver_data - capabilities for the mmsys + * @main_path: path of the main display + * @main_len: length of the main display path + * @ext_path: path of the external display + * @ext_len: length of the external display path + * @third_path: path of the third display + * @third_len: length of the third display path + * @conn_routes: routing table of all the possible connectors + * @conn_routes_num: number of the routing table for the connectors + * @shadow_register: whether or not shadow register is enabled + * @mmsys_id: multi-media system ID + * @mmsys_dev_num: number of devices for in the mmsys as a whole + * @max_pitch: maximum pitch in bytes that the mmsys supports + */ struct mtk_mmsys_driver_data { const unsigned int *main_path; unsigned int main_len; @@ -41,6 +56,8 @@ struct mtk_mmsys_driver_data { bool shadow_register; unsigned int mmsys_id; unsigned int mmsys_dev_num; + + u32 max_pitch; }; struct mtk_drm_private {