Message ID | 20231016064346.31451-3-yunfei.dong@mediatek.com |
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Mon, 16 Oct 2023 14:43:51 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 16 Oct 2023 14:43:50 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 16 Oct 2023 14:43:49 +0800 From: Yunfei Dong <yunfei.dong@mediatek.com> To: =?utf-8?q?N=C3=ADcolas_F_=2E_R_=2E_A_=2E_Prado?= <nfraprado@collabora.com>, Nicolas Dufresne <nicolas.dufresne@collabora.com>, Hans Verkuil <hverkuil-cisco@xs4all.nl>, AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>, Benjamin Gaignard <benjamin.gaignard@collabora.com>, Nathan Hebert <nhebert@chromium.org> CC: Chen-Yu Tsai <wenst@chromium.org>, Hsin-Yi Wang <hsinyi@chromium.org>, Fritz Koenig <frkoenig@chromium.org>, Daniel Vetter <daniel@ffwll.ch>, Steve Cho <stevecho@chromium.org>, Yunfei Dong <yunfei.dong@mediatek.com>, <linux-media@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-mediatek@lists.infradead.org>, <Project_Global_Chrome_Upstream_Group@mediatek.com> Subject: [PATCH 3/7] media: mediatek: vcodec: Setting the supported h265 level for each platform Date: Mon, 16 Oct 2023 14:43:42 +0800 Message-ID: <20231016064346.31451-3-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231016064346.31451-1-yunfei.dong@mediatek.com> References: <20231016064346.31451-1-yunfei.dong@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-MTK: N X-Spam-Status: No, score=-0.3 required=5.0 tests=APP_DEVELOPMENT_NORDNS, BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,RDNS_NONE,SPF_HELO_PASS,T_SPF_TEMPERROR, UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); 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Series |
[1/7] media: mediatek: vcodec: Getting the chip name of each platform
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Commit Message
Yunfei Dong (董云飞)
Oct. 16, 2023, 6:43 a.m. UTC
The supported resolution and fps of different platforms are not the
same. Need to set the supported level according to the chip name.
Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
---
.../vcodec/decoder/mtk_vcodec_dec_stateless.c | 28 +++++++++++++++++++
1 file changed, 28 insertions(+)
Comments
Hey Yunfei, On 16.10.2023 14:43, Yunfei Dong wrote: >The supported resolution and fps of different platforms are not the >same. Need to set the supported level according to the chip name. I would suggest the following rewording: Set the maximum H265 codec level for each platform. The various mediatek platforms support different levels for decoding, the level of the codec limits among others the maximum resolution, bit rate and frame rate for the decoder. With that you can add: Reviewed-by: Sebastian Fricke <sebastian.fricke@collabora.com> Regards, Sebastian >Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com> >--- > .../vcodec/decoder/mtk_vcodec_dec_stateless.c | 28 +++++++++++++++++++ > 1 file changed, 28 insertions(+) > >diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c >index f4af81bddc58..1fdb21dbacb8 100644 >--- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c >+++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c >@@ -147,6 +147,16 @@ static const struct mtk_stateless_control mtk_stateless_controls[] = { > }, > .codec_type = V4L2_PIX_FMT_HEVC_SLICE, > }, >+ { >+ .cfg = { >+ .id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, >+ .min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1, >+ .def = V4L2_MPEG_VIDEO_HEVC_LEVEL_4, >+ .max = V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1, >+ }, >+ .codec_type = V4L2_PIX_FMT_HEVC_SLICE, >+ }, >+ > { > .cfg = { > .id = V4L2_CID_STATELESS_HEVC_DECODE_MODE, >@@ -549,6 +559,20 @@ static void mtk_vcodec_dec_fill_h264_level(struct v4l2_ctrl_config *cfg, > }; > } > >+static void mtk_vcodec_dec_fill_h265_level(struct v4l2_ctrl_config *cfg, >+ struct mtk_vcodec_dec_ctx *ctx) >+{ >+ switch (ctx->dev->chip_name) { >+ case MTK_VDEC_MT8188: >+ case MTK_VDEC_MT8195: >+ cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1; >+ break; >+ default: >+ cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_4; >+ break; >+ }; >+} >+ > static void mtk_vcodec_dec_reset_controls(struct v4l2_ctrl_config *cfg, > struct mtk_vcodec_dec_ctx *ctx) > { >@@ -557,6 +581,10 @@ static void mtk_vcodec_dec_reset_controls(struct v4l2_ctrl_config *cfg, > mtk_vcodec_dec_fill_h264_level(cfg, ctx); > mtk_v4l2_vdec_dbg(3, ctx, "h264 supported level: %lld %lld", cfg->max, cfg->def); > break; >+ case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL: >+ mtk_vcodec_dec_fill_h265_level(cfg, ctx); >+ mtk_v4l2_vdec_dbg(3, ctx, "h265 supported level: %lld %lld", cfg->max, cfg->def); >+ break; > default: > break; > }; >-- >2.18.0 >
Hey Yunfei, please replace Setting with Set in the title. On 21.10.2023 11:25, Sebastian Fricke wrote: >Hey Yunfei, > >On 16.10.2023 14:43, Yunfei Dong wrote: >>The supported resolution and fps of different platforms are not the >>same. Need to set the supported level according to the chip name. > >I would suggest the following rewording: > >Set the maximum H265 codec level for each platform. >The various mediatek platforms support different levels for decoding, >the level of the codec limits among others the maximum resolution, bit >rate and frame rate for the decoder. > >With that you can add: >Reviewed-by: Sebastian Fricke <sebastian.fricke@collabora.com> > >Regards, >Sebastian > >>Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com> >>--- >>.../vcodec/decoder/mtk_vcodec_dec_stateless.c | 28 +++++++++++++++++++ >>1 file changed, 28 insertions(+) >> >>diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c >>index f4af81bddc58..1fdb21dbacb8 100644 >>--- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c >>+++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c >>@@ -147,6 +147,16 @@ static const struct mtk_stateless_control mtk_stateless_controls[] = { >> }, >> .codec_type = V4L2_PIX_FMT_HEVC_SLICE, >> }, >>+ { >>+ .cfg = { >>+ .id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, >>+ .min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1, >>+ .def = V4L2_MPEG_VIDEO_HEVC_LEVEL_4, >>+ .max = V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1, >>+ }, >>+ .codec_type = V4L2_PIX_FMT_HEVC_SLICE, >>+ }, >>+ >> { >> .cfg = { >> .id = V4L2_CID_STATELESS_HEVC_DECODE_MODE, >>@@ -549,6 +559,20 @@ static void mtk_vcodec_dec_fill_h264_level(struct v4l2_ctrl_config *cfg, >> }; >>} >> >>+static void mtk_vcodec_dec_fill_h265_level(struct v4l2_ctrl_config *cfg, >>+ struct mtk_vcodec_dec_ctx *ctx) >>+{ >>+ switch (ctx->dev->chip_name) { >>+ case MTK_VDEC_MT8188: >>+ case MTK_VDEC_MT8195: >>+ cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1; >>+ break; >>+ default: >>+ cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_4; >>+ break; >>+ }; >>+} >>+ >>static void mtk_vcodec_dec_reset_controls(struct v4l2_ctrl_config *cfg, >> struct mtk_vcodec_dec_ctx *ctx) >>{ >>@@ -557,6 +581,10 @@ static void mtk_vcodec_dec_reset_controls(struct v4l2_ctrl_config *cfg, >> mtk_vcodec_dec_fill_h264_level(cfg, ctx); >> mtk_v4l2_vdec_dbg(3, ctx, "h264 supported level: %lld %lld", cfg->max, cfg->def); >> break; >>+ case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL: >>+ mtk_vcodec_dec_fill_h265_level(cfg, ctx); >>+ mtk_v4l2_vdec_dbg(3, ctx, "h265 supported level: %lld %lld", cfg->max, cfg->def); >>+ break; >> default: >> break; >> }; >>-- >>2.18.0 >>
diff --git a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c index f4af81bddc58..1fdb21dbacb8 100644 --- a/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c +++ b/drivers/media/platform/mediatek/vcodec/decoder/mtk_vcodec_dec_stateless.c @@ -147,6 +147,16 @@ static const struct mtk_stateless_control mtk_stateless_controls[] = { }, .codec_type = V4L2_PIX_FMT_HEVC_SLICE, }, + { + .cfg = { + .id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, + .min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1, + .def = V4L2_MPEG_VIDEO_HEVC_LEVEL_4, + .max = V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1, + }, + .codec_type = V4L2_PIX_FMT_HEVC_SLICE, + }, + { .cfg = { .id = V4L2_CID_STATELESS_HEVC_DECODE_MODE, @@ -549,6 +559,20 @@ static void mtk_vcodec_dec_fill_h264_level(struct v4l2_ctrl_config *cfg, }; } +static void mtk_vcodec_dec_fill_h265_level(struct v4l2_ctrl_config *cfg, + struct mtk_vcodec_dec_ctx *ctx) +{ + switch (ctx->dev->chip_name) { + case MTK_VDEC_MT8188: + case MTK_VDEC_MT8195: + cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1; + break; + default: + cfg->max = V4L2_MPEG_VIDEO_HEVC_LEVEL_4; + break; + }; +} + static void mtk_vcodec_dec_reset_controls(struct v4l2_ctrl_config *cfg, struct mtk_vcodec_dec_ctx *ctx) { @@ -557,6 +581,10 @@ static void mtk_vcodec_dec_reset_controls(struct v4l2_ctrl_config *cfg, mtk_vcodec_dec_fill_h264_level(cfg, ctx); mtk_v4l2_vdec_dbg(3, ctx, "h264 supported level: %lld %lld", cfg->max, cfg->def); break; + case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL: + mtk_vcodec_dec_fill_h265_level(cfg, ctx); + mtk_v4l2_vdec_dbg(3, ctx, "h265 supported level: %lld %lld", cfg->max, cfg->def); + break; default: break; };