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Tue, 17 Oct 2023 03:11:29 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 39H3BSJO015405 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 17 Oct 2023 03:11:28 GMT Received: from hu-bjorande-lv.qualcomm.com (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Mon, 16 Oct 2023 20:11:28 -0700 From: Bjorn Andersson Date: Mon, 16 Oct 2023 20:11:16 -0700 Subject: [PATCH 08/12] usb: dwc3: qcom: Inline the qscratch constants MIME-Version: 1.0 Message-ID: <20231016-dwc3-refactor-v1-8-ab4a84165470@quicinc.com> References: <20231016-dwc3-refactor-v1-0-ab4a84165470@quicinc.com> In-Reply-To: <20231016-dwc3-refactor-v1-0-ab4a84165470@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , Thinh Nguyen , Felipe Balbi , Philipp Zabel CC: , , , , Johan Hovold , Krishna Kurapati PSSNV , "Bjorn Andersson" X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; 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Mon, 16 Oct 2023 20:13:07 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779970753926963671 X-GMAIL-MSGID: 1779970753926963671 The two constants for the offset and size of the qscratch block within the DWC3 region has the same value in all supported variants, so they don't necessarily need to be picked dynamically. By replacing the lookup with the constants it's possible to reuse the same code path without the ACPI pdata structure in the upcoming commit. Signed-off-by: Bjorn Andersson Reviewed-by: Konrad Dybcio --- drivers/usb/dwc3/dwc3-qcom.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c index cc0fe010ee8c..cf6c391ba498 100644 --- a/drivers/usb/dwc3/dwc3-qcom.c +++ b/drivers/usb/dwc3/dwc3-qcom.c @@ -54,8 +54,6 @@ #define APPS_USB_PEAK_BW MBps_to_icc(40) struct dwc3_acpi_pdata { - u32 qscratch_base_offset; - u32 qscratch_base_size; int hs_phy_irq_index; int dp_hs_phy_irq_index; int dm_hs_phy_irq_index; @@ -859,10 +857,8 @@ static int dwc3_qcom_probe(struct platform_device *pdev) memcpy(&local_res, res, sizeof(struct resource)); parent_res = &local_res; - parent_res->start = res->start + - qcom->acpi_pdata->qscratch_base_offset; - parent_res->end = parent_res->start + - qcom->acpi_pdata->qscratch_base_size; + parent_res->start = res->start + SDM845_QSCRATCH_BASE_OFFSET; + parent_res->end = parent_res->start + SDM845_QSCRATCH_SIZE; } qcom->qscratch_base = devm_ioremap_resource(dev, parent_res); @@ -1073,8 +1069,6 @@ MODULE_DEVICE_TABLE(of, dwc3_qcom_of_match); #ifdef CONFIG_ACPI static const struct dwc3_acpi_pdata sdm845_acpi_pdata = { - .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET, - .qscratch_base_size = SDM845_QSCRATCH_SIZE, .hs_phy_irq_index = 1, .dp_hs_phy_irq_index = 4, .dm_hs_phy_irq_index = 3, @@ -1082,8 +1076,6 @@ static const struct dwc3_acpi_pdata sdm845_acpi_pdata = { }; static const struct dwc3_acpi_pdata sdm845_acpi_urs_pdata = { - .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET, - .qscratch_base_size = SDM845_QSCRATCH_SIZE, .hs_phy_irq_index = 1, .dp_hs_phy_irq_index = 4, .dm_hs_phy_irq_index = 3,