diff mbox series

[v2] riscv: dts: starfive: visionfive 2: correct spi's ss pin

Message ID 20231012091729.3fzfDD1I@linutronix.de
State New
Headers
Series [v2] riscv: dts: starfive: visionfive 2: correct spi's ss pin |

Commit Message

Nam Cao Oct. 12, 2023, 9:17 a.m. UTC 
  The ss pin of spi0 is the same as sck pin. According to the
visionfive 2 documentation, it should be pin 49 instead of 48.

Fixes: 74fb20c8f05d ("riscv: dts: starfive: Add spi node and pins configuration")
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Nam Cao <namcao@linutronix.de>
---
v2: resend due to email problem

 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Conor Dooley Oct. 12, 2023, 9:24 a.m. UTC | #1 
From: Conor Dooley <conor.dooley@microchip.com>

On Thu, 12 Oct 2023 11:17:29 +0200, Nam Cao wrote:
> The ss pin of spi0 is the same as sck pin. According to the
> visionfive 2 documentation, it should be pin 49 instead of 48.
> 
> 

Applied to riscv-dt-fixes, thanks!

[1/1] riscv: dts: starfive: visionfive 2: correct spi's ss pin
      https://git.kernel.org/conor/c/cf98fe6b579e

Thanks,
Conor.
diff mbox series

Patch

diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 12ebe9792356..2c02358abd71 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -431,7 +431,7 @@  GPOEN_ENABLE,
 		};
 
 		ss-pins {
-			pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_FSS,
+			pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS,
 					      GPOEN_ENABLE,
 					      GPI_SYS_SPI0_FSS)>;
 			bias-disable;