From patchwork Wed Oct 11 11:14:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 151314 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp462700vqb; Wed, 11 Oct 2023 04:21:28 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEwKtD89NUiHgrSfkW5NQkqeqEJlzTJg0wZ0K9Wa4w900W3Zyz8oKWSax8PWH5zxUjNJGUM X-Received: by 2002:a05:6a20:3d04:b0:13d:d5bd:758f with SMTP id y4-20020a056a203d0400b0013dd5bd758fmr25833803pzi.6.1697023287756; Wed, 11 Oct 2023 04:21:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697023287; cv=none; d=google.com; s=arc-20160816; b=m7c9pW4LxpqbdoSNkVzVPaQ2hc2oSVwKuq+S4QJz9N24xGQ/km0IxtXq2V/6L5RPcZ pJH6QiC9mSFc/j4uxuoExAmFEpXoM0MqnYT7oA4UkUGxigOpA+LuDiHM1bmHes85KhFw /aiI0xrZCI0wiff+GKBI5GWyEut8QeoSIB3ZLER4xiFLSaGuQ9gWpRJrJyB9/9QiEQTb i8pXO0QWx0V/Faxy5cxrebCXXlWe6hfPeCe3DbIaqRnWI+vx7ITG/yEeMrCLdMAzL+GC AoqzfUuHiaz2VINF/ifUTjnJrQDhpJh+MMqV9cS9t4g4l/SEYOm61SWOOjT0ToRjZZR1 60bQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=eAZEvLYxGtlCREP0d8aetAY70GgHX4OI1AI4HHQY6l8=; fh=YTBEzcO0MYpF5YfD8pS5vr0pvVavk2TCgoIFkI+x0fk=; b=wbN+eygoI8JOY4+wET3pPWJqySCg1XzoCynCYALpECWUZ5B0y/uW5nEZYW4IjnR6qd 82NdHnP7P6scjGGN+ykONww4wo9U9T1KX8+pazZDNMuYikvPC72pLvPwXwFgEgop+0Wj ykxIxrndayHPscANghambVFHI/vbYvPDJOZpnNR73FT3CePcRxNzkOdMzHyRHUHsRZSA x3HOP4Rh35bPGrEMc7bGocQloda3/pVI4UZuUOBKGOEUWfma9oimFf7gBOC78wK1qzYo 9ZVxf3hA/T9ECyEZKTntWwA5qyxsdB9nmiPMYsBZZ5oc9RDxNS2x8pZ0ry9YFe/B+O+r r+rg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=WBq8ggfx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from lipwig.vger.email (lipwig.vger.email. [2620:137:e000::3:3]) by mx.google.com with ESMTPS id z16-20020a656650000000b00578c4d1f530si13974935pgv.728.2023.10.11.04.21.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 04:21:27 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) client-ip=2620:137:e000::3:3; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=WBq8ggfx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 84A0A80B4208; Wed, 11 Oct 2023 04:20:16 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234690AbjJKLT6 (ORCPT + 18 others); Wed, 11 Oct 2023 07:19:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34940 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231916AbjJKLTV (ORCPT ); Wed, 11 Oct 2023 07:19:21 -0400 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D369B8F for ; Wed, 11 Oct 2023 04:19:18 -0700 (PDT) Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-405e48d8e72so11541105e9.0 for ; Wed, 11 Oct 2023 04:19:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697023157; x=1697627957; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eAZEvLYxGtlCREP0d8aetAY70GgHX4OI1AI4HHQY6l8=; b=WBq8ggfxp30QHg4C6ifpBEl57tD72Bbc0k0P/8EbmqyytjjXiuuQJ4oUl9Zf+J+ueH NHNRFPZiiA+jhHBX79pe2ydrTgNvqPgzFNQ4tvzLF1zYZnG0k2kKOobwYd+nAgdVNuFc BTEGHMonsr3Vl4j2mFbuQeTtqUJ7r6dDuWO/8seofD/vhCe6lua7Ht40fiDvY4BcF63W 95WRcOjFZ3+rthO9leIfBrihlEc74reo7nv9IMgv1LqgmEpObryTkdNumbkEiFtSB/h8 Oa/RMCvc76z76kSCP7HRW5Kywfy4HctKVfI3gRayvQdxbQcwahu0lyvBfI5fBEKWCFvd jxJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697023157; x=1697627957; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eAZEvLYxGtlCREP0d8aetAY70GgHX4OI1AI4HHQY6l8=; b=OejMcPklfwQzzk6r38bKesz1mUf90pob9YxdzScyPLTX6OpQVWO90qESXS83KKX1vk fXB3sZXjwIFrjH2rHgaqBK32EOAdKlVuGZk2v+qlSOx+7SMfeP9XzkvOUMboU6hAo7QN JTUimg+CmJYVN0PMf0jmlxJzb8pHfpF9r/lpnVsh/ls8qFKqOkqoFMLAEwwpNOy061NN zMloXjsh2pjENF9UcodAC8bdpbTHo1tTISK1NZ+25agAx8Gf94StYYveIzoRFABBcTQx 5y+Ppj83ju2f6zHiqBMWVpsk4tVEh1S7LC3e9zuntLfjy7CRoGT0hsfctq5OY0s4NwfA 15QQ== X-Gm-Message-State: AOJu0Yy1JE/1sN8J0vbdztMV86BydDrO1qrRJPED8br0p74JTahoyHwM nYKaGF4fxziIbaMdEsLfiNgGRw== X-Received: by 2002:a05:600c:1c0f:b0:405:4721:800 with SMTP id j15-20020a05600c1c0f00b0040547210800mr18701454wms.1.1697023156575; Wed, 11 Oct 2023 04:19:16 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:9134:b302:d8b:a200]) by smtp.gmail.com with ESMTPSA id a4-20020a05600c224400b003fe2b081661sm18945715wmm.30.2023.10.11.04.19.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 04:19:16 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Albert Ou , Jonathan Corbet , Andrew Jones , Evan Green , Conor Dooley Subject: [PATCH v1 03/13] riscv: hwprobe: export Zv* ISA extensions Date: Wed, 11 Oct 2023 13:14:28 +0200 Message-ID: <20231011111438.909552-4-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231011111438.909552-1-cleger@rivosinc.com> References: <20231011111438.909552-1-cleger@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=2.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RCVD_IN_SBL_CSS, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Wed, 11 Oct 2023 04:20:16 -0700 (PDT) X-Spam-Level: ** X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779457890743445373 X-GMAIL-MSGID: 1779457890743445373 Export Zv* ISA extensions that were added in "RISC-V Cryptography Extensions Volume II" specification[1] through hwprobe. This adds support for the following instructions: - Zvbb: Vector Basic Bit-manipulation - Zvbc: Vector Carryless Multiplication - Zvkb: Vector Cryptography Bit-manipulation - Zvkg: Vector GCM/GMAC. - Zvkned: NIST Suite: Vector AES Block Cipher - Zvknh[ab]: NIST Suite: Vector SHA-2 Secure Hash - Zvksed: ShangMi Suite: SM4 Block Cipher - Zvksh: ShangMi Suite: SM3 Secure Hash - Zvkn: NIST Algorithm Suite - Zvknc: NIST Algorithm Suite with carryless multiply - Zvkng: NIST Algorithm Suite with GCM. - Zvks: ShangMi Algorithm Suite - Zvksc: ShangMi Algorithm Suite with carryless multiplication - Zvksg: ShangMi Algorithm Suite with GCM. - Zvkt: Vector Data-Independent Execution Latency. [1] https://drive.google.com/file/d/1gb9OLH-DhbCgWp7VwpPOVrrY6f3oSJLL/view Signed-off-by: Clément Léger --- Documentation/riscv/hwprobe.rst | 48 +++++++++++++++++++++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 16 +++++++++ arch/riscv/kernel/sys_riscv.c | 19 +++++++++++ 3 files changed, 83 insertions(+) diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst index a52996b22f75..edfed33669ea 100644 --- a/Documentation/riscv/hwprobe.rst +++ b/Documentation/riscv/hwprobe.rst @@ -77,6 +77,54 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined in version 1.0 of the Bit-Manipulation ISA extensions. + * :c:macro:`RISCV_HWPROBE_EXT_ZVBB`: The Zvbb extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVBC`: The Zvbc extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKB`: The Zvkb extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKG`: The Zvkg extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKN`: The Zvkn extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKNC`: The Zvknc extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKNED`: The Zvkned extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKNG`: The Zvkng extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKNHA`: The Zvknha extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKNHB`: The Zvknhb extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKS`: The Zvks extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKSC`: The Zvksc extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKSED`: The Zvksed extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKSH`: The Zvksh extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKSG`: The Zvksg extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported as + defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 006bfb48343d..d868eb431cd6 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -29,6 +29,22 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZBA (1 << 3) #define RISCV_HWPROBE_EXT_ZBB (1 << 4) #define RISCV_HWPROBE_EXT_ZBS (1 << 5) +#define RISCV_HWPROBE_EXT_ZVBB (1 << 6) +#define RISCV_HWPROBE_EXT_ZVBC (1 << 7) +#define RISCV_HWPROBE_EXT_ZVKB (1 << 8) +#define RISCV_HWPROBE_EXT_ZVKG (1 << 9) +#define RISCV_HWPROBE_EXT_ZVKN (1 << 10) +#define RISCV_HWPROBE_EXT_ZVKNC (1 << 11) +#define RISCV_HWPROBE_EXT_ZVKNED (1 << 12) +#define RISCV_HWPROBE_EXT_ZVKNG (1 << 13) +#define RISCV_HWPROBE_EXT_ZVKNHA (1 << 14) +#define RISCV_HWPROBE_EXT_ZVKNHB (1 << 15) +#define RISCV_HWPROBE_EXT_ZVKS (1 << 16) +#define RISCV_HWPROBE_EXT_ZVKSC (1 << 17) +#define RISCV_HWPROBE_EXT_ZVKSED (1 << 18) +#define RISCV_HWPROBE_EXT_ZVKSH (1 << 19) +#define RISCV_HWPROBE_EXT_ZVKSG (1 << 20) +#define RISCV_HWPROBE_EXT_ZVKT (1 << 21) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 5ce593ce07a4..4f5e51c192d5 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -156,6 +156,25 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, CHECK_ISA_EXT(ZBA); CHECK_ISA_EXT(ZBB); CHECK_ISA_EXT(ZBS); + + if (has_vector()) { + CHECK_ISA_EXT(ZVBB); + CHECK_ISA_EXT(ZVBC); + CHECK_ISA_EXT(ZVKB); + CHECK_ISA_EXT(ZVKG); + CHECK_ISA_EXT(ZVKN); + CHECK_ISA_EXT(ZVKNC); + CHECK_ISA_EXT(ZVKNED); + CHECK_ISA_EXT(ZVKNG); + CHECK_ISA_EXT(ZVKNHA); + CHECK_ISA_EXT(ZVKNHB); + CHECK_ISA_EXT(ZVKS); + CHECK_ISA_EXT(ZVKSC); + CHECK_ISA_EXT(ZVKSED); + CHECK_ISA_EXT(ZVKSH); + CHECK_ISA_EXT(ZVKSG); + CHECK_ISA_EXT(ZVKT); + } #undef CHECK_ISA_EXT }