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Tue, 10 Oct 2023 15:03:08 -0500 From: John Allen To: CC: , , , , , , , , John Allen Subject: [PATCH 3/9] KVM: x86: SVM: Pass through shadow stack MSRs Date: Tue, 10 Oct 2023 20:02:14 +0000 Message-ID: <20231010200220.897953-4-john.allen@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231010200220.897953-1-john.allen@amd.com> References: <20231010200220.897953-1-john.allen@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003440:EE_|CY8PR12MB7242:EE_ X-MS-Office365-Filtering-Correlation-Id: 7e616259-a969-48ba-6716-08dbc9cbecbf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: dwhSFk1V+y1oT/0xDrqkFI5ZkoUjDVmV2F5EYmDLTl7/d/c35AW+yN/WisXGCq7g0qxEyp8bHKx/j0SvfL5sYQnekSg050h09FCD/Bl84y8o7oSsKOjdaVGgxDOj7Mgyn/OnvGFjwMqtDnuQCbNcAgw0qk8BZE+nTEMPtN3+gxw5b0nUjUhvb9jcw85Egwn/h6JFTME3OO/ReA/wQyFEJiZ3jbkPkV7tqpcvFbg2ACkfK51UqZD3oC/rDSg8uGzwzZayc53kMfNFIU5R/UXJaEcFcAmEsfUe2m8X2g9LV9F0l1J20iyFECoBt5s0xC2oOA1ufaWYKZEsfR6pvyM0m4Janqg+jw2xeqQxDuqpOiWA26dnCdQDHWq/VuiXTD1lUuOOpcWrgtzS4KB8bIyipDz9k3ZTdEj+AlhDSr82n6Ryxj5r930ybnyILSriAWwrz0lIYZmJ5erS1Wrl3+PPG9XXObfbTP9mnNKPgjeJIsvKSVOJYoL0DD3TuBqUx1WEWlyH2GOItXpiegXe7CCzuHt1+JRQgFVGCNZ5+WSuIMMOFKFostqPzeKiYEqJYkCPXom8PANrvxald9Y+v0u/6hAkLaO2isQ8IFobPfV9n0nBsRDTisAAM+9+gaaLcL4YmGYA3OpP/gX8LorqWNbsuOdTR8uIQEuxyrYoAkGGan1HnaH6mFeOxrl44lBqyvCD6L091AYqjJpZkai/8QCmedfIQbhbbFdq5Eo9xQsFs75E4wwyWS7EdccvrP0tbAjKvxENkfx4YGGZVq1nNRVKtg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(376002)(136003)(396003)(39860400002)(346002)(230922051799003)(186009)(451199024)(64100799003)(1800799009)(82310400011)(36840700001)(40470700004)(46966006)(6666004)(83380400001)(16526019)(426003)(26005)(336012)(2616005)(1076003)(5660300002)(81166007)(82740400003)(86362001)(40460700003)(40480700001)(36756003)(356005)(4326008)(478600001)(44832011)(2906002)(8676002)(7696005)(36860700001)(47076005)(8936002)(41300700001)(316002)(6916009)(70206006)(70586007)(54906003)(36900700001);DIR:OUT;SFP:1101; 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Tue, 10 Oct 2023 13:03:24 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779400133215681711 X-GMAIL-MSGID: 1779400133215681711 If kvm supports shadow stack, pass through shadow stack MSRs to improve guest performance. Signed-off-by: John Allen Reviewed-by: Maxim Levitsky --- arch/x86/kvm/svm/svm.c | 26 ++++++++++++++++++++++++++ arch/x86/kvm/svm/svm.h | 2 +- 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index e435e4fbadda..984e89d7a734 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -139,6 +139,13 @@ static const struct svm_direct_access_msrs { { .index = X2APIC_MSR(APIC_TMICT), .always = false }, { .index = X2APIC_MSR(APIC_TMCCT), .always = false }, { .index = X2APIC_MSR(APIC_TDCR), .always = false }, + { .index = MSR_IA32_U_CET, .always = false }, + { .index = MSR_IA32_S_CET, .always = false }, + { .index = MSR_IA32_INT_SSP_TAB, .always = false }, + { .index = MSR_IA32_PL0_SSP, .always = false }, + { .index = MSR_IA32_PL1_SSP, .always = false }, + { .index = MSR_IA32_PL2_SSP, .always = false }, + { .index = MSR_IA32_PL3_SSP, .always = false }, { .index = MSR_INVALID, .always = false }, }; @@ -1225,6 +1232,25 @@ static inline void init_vmcb_after_set_cpuid(struct kvm_vcpu *vcpu) set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 1, 1); set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 1, 1); } + + if (kvm_cpu_cap_has(X86_FEATURE_SHSTK)) { + bool shstk_enabled = guest_cpuid_has(vcpu, X86_FEATURE_SHSTK); + + set_msr_interception(vcpu, svm->msrpm, MSR_IA32_U_CET, + shstk_enabled, shstk_enabled); + set_msr_interception(vcpu, svm->msrpm, MSR_IA32_S_CET, + shstk_enabled, shstk_enabled); + set_msr_interception(vcpu, svm->msrpm, MSR_IA32_INT_SSP_TAB, + shstk_enabled, shstk_enabled); + set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PL0_SSP, + shstk_enabled, shstk_enabled); + set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PL1_SSP, + shstk_enabled, shstk_enabled); + set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PL2_SSP, + shstk_enabled, shstk_enabled); + set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PL3_SSP, + shstk_enabled, shstk_enabled); + } } static void init_vmcb(struct kvm_vcpu *vcpu) diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index f41253958357..bdc39003b955 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -30,7 +30,7 @@ #define IOPM_SIZE PAGE_SIZE * 3 #define MSRPM_SIZE PAGE_SIZE * 2 -#define MAX_DIRECT_ACCESS_MSRS 46 +#define MAX_DIRECT_ACCESS_MSRS 53 #define MSRPM_OFFSETS 32 extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; extern bool npt_enabled;