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Mon, 09 Oct 2023 09:36:27 -0700 (PDT) From: Neil Armstrong Date: Mon, 09 Oct 2023 18:36:16 +0200 Subject: [PATCH RFC 5/5] drm/msm: dpu1: sm8550: move split clock controls to sspp entries MIME-Version: 1.0 Message-Id: <20231009-topic-sm8550-graphics-sspp-split-clk-v1-5-806c0dee4e43@linaro.org> References: <20231009-topic-sm8550-graphics-sspp-split-clk-v1-0-806c0dee4e43@linaro.org> In-Reply-To: <20231009-topic-sm8550-graphics-sspp-split-clk-v1-0-806c0dee4e43@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=4767; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=rXNZZh0U0CRAs1SezapHV4WxBUWrXsKmahG1hZ3zZNk=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBlJCwFnTWJsAER2yIeZLeIaUwvwtPF1lWZA63oFT6P DsY8haGJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZSQsBQAKCRB33NvayMhJ0booEA C52PH6JsPH69GimG9O/TqLJm6uLT1CP6O3DeHBomQYq0jcGdx8SsMpd9yab6ud4JwRN2oZGrgx2TS+ RBP0cyFrJMkcgA4gV8Afp0f2Slm93eHOuY42noW3SMZbQPR9kHJK69Ge6rHTta68xSkht/nBK+VHUj w8MWu/F0nrfeqg84un8/49Dgfvhabsd8y1z9NiLkDP3LiLb5FVT/cvFeNJp9Jaxml4voxVYiOPhC2o w2cKb5WD0hWsZxfhydbAEstT13Yhol8gS4xiFw0kZxok3WbCLyVNYZwawhOr5VIMRFlORGB3RcxTcT REZYAmnpEHbhxYahqRkINTxO6VW3OXiCwjZ58j5hnLoUJIY2ANWNm6pqIWMOTU2xUPOaLak4P62TYI M0T8Aks+0wDo6oSJaMlRMpoCTMOhuy81LEt/6WKJkHLVi3+l7MNAhL2bjOoB3yI1ZGbG4XW+oei90O EwsqSKtkfl3xudznsZAi2zZ+0/hS7vS942SPpAuQPRib9V8O1krzhBsVUsgAwETcTGT9qas+6FxRPT 1qg6kHR4+dKtsHnCO/k5sSswGqcqAGVINqQ5jooKdODzKTee6rs0fGMOsMdM4UkXDLZkgw2FaOCx8G aMxyCKlvisLiLQGFC50u5k/dYk9Zus3NUQb6G80WKB58J5PhX/LGm/Pzm9kA== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE X-Spam-Status: No, score=2.7 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Mon, 09 Oct 2023 09:37:14 -0700 (PDT) X-Spam-Level: ** X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779296567645979075 X-GMAIL-MSGID: 1779296567645979075 The SM8550 has the SSPP clk_ctrl in the SSPP registers, move them out of the MDP top. Signed-off-by: Neil Armstrong --- .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 35 ++++++++++------------ 1 file changed, 15 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 7bed819dfc39..527ec020fba4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -24,16 +24,6 @@ static const struct dpu_mdp_cfg sm8550_mdp = { .base = 0, .len = 0x494, .features = BIT(DPU_MDP_PERIPH_0_REMOVED), .clk_ctrls = { - [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x4330, .bit_off = 0 }, - [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x6330, .bit_off = 0 }, - [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x8330, .bit_off = 0 }, - [DPU_CLK_CTRL_VIG3] = { .reg_off = 0xa330, .bit_off = 0 }, - [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x24330, .bit_off = 0 }, - [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x26330, .bit_off = 0 }, - [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x28330, .bit_off = 0 }, - [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2a330, .bit_off = 0 }, - [DPU_CLK_CTRL_DMA4] = { .reg_off = 0x2c330, .bit_off = 0 }, - [DPU_CLK_CTRL_DMA5] = { .reg_off = 0x2e330, .bit_off = 0 }, [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, }, }; @@ -73,6 +63,11 @@ static const struct dpu_ctl_cfg sm8550_ctl[] = { }, }; +static const struct dpu_clk_ctrl_reg sm8550_sspp_clk_ctrl = { + .reg_off = 0x330, + .bit_off = 0 +}; + static const struct dpu_sspp_cfg sm8550_sspp[] = { { .name = "sspp_0", .id = SSPP_VIG0, @@ -81,7 +76,7 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { .sblk = &sm8550_vig_sblk_0, .xin_id = 0, .type = SSPP_TYPE_VIG, - .clk_ctrl = DPU_CLK_CTRL_VIG0, + .clk_ctrl_reg = &sm8550_sspp_clk_ctrl, }, { .name = "sspp_1", .id = SSPP_VIG1, .base = 0x6000, .len = 0x344, @@ -89,7 +84,7 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { .sblk = &sm8550_vig_sblk_1, .xin_id = 4, .type = SSPP_TYPE_VIG, - .clk_ctrl = DPU_CLK_CTRL_VIG1, + .clk_ctrl_reg = &sm8550_sspp_clk_ctrl, }, { .name = "sspp_2", .id = SSPP_VIG2, .base = 0x8000, .len = 0x344, @@ -97,7 +92,7 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { .sblk = &sm8550_vig_sblk_2, .xin_id = 8, .type = SSPP_TYPE_VIG, - .clk_ctrl = DPU_CLK_CTRL_VIG2, + .clk_ctrl_reg = &sm8550_sspp_clk_ctrl, }, { .name = "sspp_3", .id = SSPP_VIG3, .base = 0xa000, .len = 0x344, @@ -105,7 +100,7 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { .sblk = &sm8550_vig_sblk_3, .xin_id = 12, .type = SSPP_TYPE_VIG, - .clk_ctrl = DPU_CLK_CTRL_VIG3, + .clk_ctrl_reg = &sm8550_sspp_clk_ctrl, }, { .name = "sspp_8", .id = SSPP_DMA0, .base = 0x24000, .len = 0x344, @@ -113,7 +108,7 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { .sblk = &sdm845_dma_sblk_0, .xin_id = 1, .type = SSPP_TYPE_DMA, - .clk_ctrl = DPU_CLK_CTRL_DMA0, + .clk_ctrl_reg = &sm8550_sspp_clk_ctrl, }, { .name = "sspp_9", .id = SSPP_DMA1, .base = 0x26000, .len = 0x344, @@ -121,7 +116,7 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { .sblk = &sdm845_dma_sblk_1, .xin_id = 5, .type = SSPP_TYPE_DMA, - .clk_ctrl = DPU_CLK_CTRL_DMA1, + .clk_ctrl_reg = &sm8550_sspp_clk_ctrl, }, { .name = "sspp_10", .id = SSPP_DMA2, .base = 0x28000, .len = 0x344, @@ -129,7 +124,7 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { .sblk = &sdm845_dma_sblk_2, .xin_id = 9, .type = SSPP_TYPE_DMA, - .clk_ctrl = DPU_CLK_CTRL_DMA2, + .clk_ctrl_reg = &sm8550_sspp_clk_ctrl, }, { .name = "sspp_11", .id = SSPP_DMA3, .base = 0x2a000, .len = 0x344, @@ -137,7 +132,7 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { .sblk = &sdm845_dma_sblk_3, .xin_id = 13, .type = SSPP_TYPE_DMA, - .clk_ctrl = DPU_CLK_CTRL_DMA3, + .clk_ctrl_reg = &sm8550_sspp_clk_ctrl, }, { .name = "sspp_12", .id = SSPP_DMA4, .base = 0x2c000, .len = 0x344, @@ -145,7 +140,7 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { .sblk = &sm8550_dma_sblk_4, .xin_id = 14, .type = SSPP_TYPE_DMA, - .clk_ctrl = DPU_CLK_CTRL_DMA4, + .clk_ctrl_reg = &sm8550_sspp_clk_ctrl, }, { .name = "sspp_13", .id = SSPP_DMA5, .base = 0x2e000, .len = 0x344, @@ -153,7 +148,7 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { .sblk = &sm8550_dma_sblk_5, .xin_id = 15, .type = SSPP_TYPE_DMA, - .clk_ctrl = DPU_CLK_CTRL_DMA5, + .clk_ctrl_reg = &sm8550_sspp_clk_ctrl, }, };