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[23.128.96.34]) by mx.google.com with ESMTPS id ju3-20020a170903428300b001bbb175a81asi1556747plb.263.2023.10.05.07.47.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Oct 2023 07:47:56 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) client-ip=23.128.96.34; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=U9GrKOnd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id 34F9C85C6CD3; Thu, 5 Oct 2023 07:46:40 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237682AbjJEOqJ (ORCPT + 19 others); Thu, 5 Oct 2023 10:46:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33410 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238995AbjJEOlb (ORCPT ); Thu, 5 Oct 2023 10:41:31 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C6543A5C7; Thu, 5 Oct 2023 07:16:18 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 395DRfYm128470; Thu, 5 Oct 2023 08:27:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1696512461; bh=s2POO6h/gtAk3EHTaudsU8u3WXVUmNWLvH3/EEsI0Gs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=U9GrKOnd4dKuSfTgA4uShEU0bUoID9b6S0HAh+CL007oxBOLGcE39tRmXROlYK/x4 kz1Pk1tB5nQTz9u2Fvehy0cUxt05yHE/IfuEAffsAfz9CxVVdxsO+dzY3l8ItuBxiL xqBT1/VZKigDnfGATC/F/Y7uVxB8YAL4A/2EGxEQ= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 395DRfwh025084 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 5 Oct 2023 08:27:41 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 5 Oct 2023 08:27:41 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 5 Oct 2023 08:27:41 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 395DReuu057448; Thu, 5 Oct 2023 08:27:41 -0500 From: Jayesh Choudhary To: , , CC: , , , , , , , , , , , , Subject: [PATCH RESEND v11 4/5] arm64: dts: ti: k3-j784s4-evm: Enable DisplayPort-0 Date: Thu, 5 Oct 2023 18:57:31 +0530 Message-ID: <20231005132732.7462-5-j-choudhary@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231005132732.7462-1-j-choudhary@ti.com> References: <20231005132732.7462-1-j-choudhary@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_PASS,SPF_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Thu, 05 Oct 2023 07:46:40 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778927300170442649 X-GMAIL-MSGID: 1778927300170442649 From: Rahul T R Enable display for J784S4 EVM. Add assigned clocks for DSS, DT node for DisplayPort PHY and pinmux for DP HPD. Add the clock frequency for serdes_refclk. Add the endpoint nodes to describe connection from: DSS => MHDP => DisplayPort connector. Also add the GPIO expander-4 node and pinmux for main_i2c4 which is required for controlling DP power. Set status for all required nodes for DP-0 as "okay". Signed-off-by: Rahul T R [j-choudhary@ti.com: move all the changes together to enable DP-0 in EVM] Signed-off-by: Jayesh Choudhary Reviewed-by: Aradhya Bhatia --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 119 +++++++++++++++++++++++ 1 file changed, 119 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index 5991c2e1d994..6f46a1ab179e 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -249,6 +249,28 @@ vdd_sd_dv: regulator-TLV71033 { states = <1800000 0x0>, <3300000 0x1>; }; + + dp0_pwr_3v3: regulator-dp0-prw { + compatible = "regulator-fixed"; + regulator-name = "dp0-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + dp0: connector-dp0 { + compatible = "dp-connector"; + label = "DP0"; + type = "full-size"; + dp-pwr-supply = <&dp0_pwr_3v3>; + + port { + dp0_connector_in: endpoint { + remote-endpoint = <&dp0_out>; + }; + }; + }; }; &main_pmx0 { @@ -289,6 +311,19 @@ vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ >; }; + + dp0_pins_default: dp0-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0cc, PIN_INPUT, 12) /* (AM37) SPI0_CS0.DP0_HPD */ + >; + }; + + main_i2c4_pins_default: main-i2c4-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AG33) MCAN14_TX.I2C4_SCL */ + J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */ + >; + }; }; &wkup_pmx2 { @@ -862,3 +897,87 @@ adc { ti,adc-channels = <0 1 2 3 4 5 6 7>; }; }; + +&serdes_refclk { + status = "okay"; + clock-frequency = <100000000>; +}; + +&dss { + status = "okay"; + assigned-clocks = <&k3_clks 218 2>, + <&k3_clks 218 5>, + <&k3_clks 218 14>, + <&k3_clks 218 18>; + assigned-clock-parents = <&k3_clks 218 3>, + <&k3_clks 218 7>, + <&k3_clks 218 16>, + <&k3_clks 218 22>; +}; + +&serdes_wiz4 { + status = "okay"; +}; + +&serdes4 { + status = "okay"; + serdes4_dp_link: phy@0 { + reg = <0>; + cdns,num-lanes = <4>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>, + <&serdes_wiz4 3>, <&serdes_wiz4 4>; + }; +}; + +&mhdp { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dp0_pins_default>; + phys = <&serdes4_dp_link>; + phy-names = "dpphy"; +}; + +&dss_ports { + /* DP */ + port@0 { + reg = <0>; + + dpi0_out: endpoint { + remote-endpoint = <&dp0_in>; + }; + }; +}; + +&main_i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c4_pins_default>; + clock-frequency = <400000>; + + exp4: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&dp0_ports { + port@0 { + reg = <0>; + + dp0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + + port@4 { + reg = <4>; + + dp0_out: endpoint { + remote-endpoint = <&dp0_connector_in>; + }; + }; +};