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Thu, 05 Oct 2023 07:06:46 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778924710887610604 X-GMAIL-MSGID: 1778924710887610604 DT binding for the PWM block in Qualcomm IPQ6018 SoC. Reviewed-by: Bjorn Andersson Reviewed-by: Krzysztof Kozlowski Co-developed-by: Baruch Siach Signed-off-by: Baruch Siach Signed-off-by: Devi Priya --- v14: Picked up the R-b tag v13: Updated the file name to match the compatible Sorted the properties and updated the order in the required field Dropped the syscon node from examples v12: Picked up the R-b tag v11: No change v10: No change v9: Add 'ranges' property to example (Rob) Drop label in example (Rob) v8: Add size cell to 'reg' (Rob) v7: Use 'reg' instead of 'offset' (Rob) Drop 'clock-names' and 'assigned-clock*' (Bjorn) Use single cell address/size in example node (Bjorn) Move '#pwm-cells' lower in example node (Bjorn) List 'reg' as required v6: Device node is child of TCSR; remove phandle (Rob Herring) Add assigned-clocks/assigned-clock-rates (Uwe Kleine-König) v5: Use qcom,pwm-regs for phandle instead of direct regs (Bjorn Andersson, Kathiravan T) v4: Update the binding example node as well (Rob Herring's bot) v3: s/qcom,pwm-ipq6018/qcom,ipq6018-pwm/ (Rob Herring) v2: Make #pwm-cells const (Rob Herring) .../bindings/pwm/qcom,ipq6018-pwm.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml diff --git a/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml b/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml new file mode 100644 index 000000000000..6d0d7ed271f7 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/qcom,ipq6018-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ6018 PWM controller + +maintainers: + - Baruch Siach + +properties: + compatible: + const: qcom,ipq6018-pwm + + reg: + description: Offset of PWM register in the TCSR block. + maxItems: 1 + + clocks: + maxItems: 1 + + "#pwm-cells": + const: 2 + +required: + - compatible + - reg + - clocks + - "#pwm-cells" + +additionalProperties: false + +examples: + - | + #include + + pwm: pwm@a010 { + compatible = "qcom,ipq6018-pwm"; + reg = <0xa010 0x20>; + clocks = <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates = <100000000>; + #pwm-cells = <2>; + };