[2/3] arm64: dts: qcom: sc7280: Add Camera Control Interface busses
Commit Message
Add the CCI busses found on sc7280 and their pinctrl states.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 136 +++++++++++++++++++++++++++++++++++
1 file changed, 136 insertions(+)
Comments
On 29.09.2023 16:15, Bryan O'Donoghue wrote:
> On 29/09/2023 14:35, Konrad Dybcio wrote:
>>
>>
>> On 9/29/23 10:01, Luca Weiss wrote:
>>> Add the CCI busses found on sc7280 and their pinctrl states.
>>>
>>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
>>> ---
>>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 136 +++++++++++++++++++++++++++++++++++
>>> 1 file changed, 136 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>>> index 66f1eb83cca7..65550de2e4ff 100644
>>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>>> @@ -3793,6 +3793,86 @@ videocc: clock-controller@aaf0000 {
>>> #power-domain-cells = <1>;
>>> };
>>> + cci0: cci@ac4a000 {
>>> + compatible = "qcom,sc7280-cci", "qcom,msm8996-cci";
>>> + reg = <0 0x0ac4a000 0 0x1000>;
>>> + interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
>>> + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
>>> +
>>> + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
>>> + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
>>> + <&camcc CAM_CC_CPAS_AHB_CLK>,
>>> + <&camcc CAM_CC_CCI_0_CLK>,
>>> + <&camcc CAM_CC_CCI_0_CLK_SRC>;
>>> + clock-names = "camnoc_axi",
>>> + "slow_ahb_src",
>>> + "cpas_ahb",
>>> + "cci",
>>> + "cci_src";
>> I guess this is more of a question to e.g. Bryan, but are all of these clocks actually necessary?
>>
>> Konrad
> Hmm its a good question, we generally take the approach of adopting all of the downstream clocks for these camera interfaces verbatim.
>
> The clock plan for this part only calls out cci_X_clk and cci_x_clk_src for the CCI however we know that to be incomplete since we *absolutely* need to have the AXI for the block clocked to access those registers, same deal with the AHB bus.
>
> AXI: registers
> AHB: data
>
> In the above list the only clock you might conceivably not need is CPAS_AHB_CLK.
>
> Let me zap that clock from sdm845 since I have an rb3 right in front of me and see what happens.
>
> Crash and reset
>
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -4402,13 +4402,11 @@ cci: cci@ac4a000 {
> clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
> <&clock_camcc CAM_CC_SOC_AHB_CLK>,
> <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
> - <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
> <&clock_camcc CAM_CC_CCI_CLK>,
> <&clock_camcc CAM_CC_CCI_CLK_SRC>;
> clock-names = "camnoc_axi",
> "soc_ahb",
> "slow_ahb_src",
> - "cpas_ahb",
> "cci",
> "cci_src";
>
>
> I think the list is good tbh
WDYT about camcc consuming ahb, like dispcc does?
AXI, hmm.. not quite sure what to do with it
Konrad
On 29/09/2023 16:25, Konrad Dybcio wrote:
>> Not actually a required clock for the clock controller.
>>
>> I suspect the same is true for dispcc and videocc though it would also mean the respective drivers would need to switch on <&gcc DISPx_CAMERA_AHB_CLK> or <&gcc GCC_VIDEO_AHB_CLK> prior to accessing registers inside the ip blocks which may not currently be the case.
>>
>> Feels like a bit of a contrary answer but my reading is the GCC_IPBLOCK_AHB_CLK clocks belong in the drivers not the clock controllers.. or at least that's true for sm8250/camcc
> I believe the idea here would be that registering GCC_IP_AHB_CLK
> as a pm_clk for the clock controller would make that clock turn
> on when IPBLOCK_CC is accessed (e.g. when we turn on
> IPBLOCK_CORE_CLK), so that it doesn't need to be duplicated in
> each and every end device.
>
> Konrad
Yeah I mean I accept the logic - the core AHB clock is effectively gated
by the ipblockcc even though they originate from different places in
hardware - and _when_ do you want one clock without the other ? Never
except at probe() time for the ipblockcc.
Then again if you can show the clock dependency tree of camera or disp
requires GCC_IP_AHB_CLK you could make the argument the dt requires the
clock dependency defined in that block.
I'd say we should offline this from Luca's patches tho :) for me anyway
the first two are fine.
Agree #3 is verboten. No new empty nodes.
---
bod
@@ -3793,6 +3793,86 @@ videocc: clock-controller@aaf0000 {
#power-domain-cells = <1>;
};
+ cci0: cci@ac4a000 {
+ compatible = "qcom,sc7280-cci", "qcom,msm8996-cci";
+ reg = <0 0x0ac4a000 0 0x1000>;
+ interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CCI_0_CLK>,
+ <&camcc CAM_CC_CCI_0_CLK_SRC>;
+ clock-names = "camnoc_axi",
+ "slow_ahb_src",
+ "cpas_ahb",
+ "cci",
+ "cci_src";
+ pinctrl-0 = <&cci0_default &cci1_default>;
+ pinctrl-1 = <&cci0_sleep &cci1_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ cci0_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci0_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cci1: cci@ac4b000 {
+ compatible = "qcom,sc7280-cci", "qcom,msm8996-cci";
+ reg = <0 0x0ac4b000 0 0x1000>;
+ interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
+ <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CCI_1_CLK>,
+ <&camcc CAM_CC_CCI_1_CLK_SRC>;
+ clock-names = "camnoc_axi",
+ "slow_ahb_src",
+ "cpas_ahb",
+ "cci",
+ "cci_src";
+ pinctrl-0 = <&cci2_default &cci3_default>;
+ pinctrl-1 = <&cci2_sleep &cci3_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ cci1_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci1_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
camcc: clock-controller@ad00000 {
compatible = "qcom,sc7280-camcc";
reg = <0 0x0ad00000 0 0x10000>;
@@ -4298,6 +4378,62 @@ tlmm: pinctrl@f100000 {
gpio-ranges = <&tlmm 0 0 175>;
wakeup-parent = <&pdc>;
+ cci0_default: cci0-default-state {
+ pins = "gpio69", "gpio70";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci0_sleep: cci0-sleep-state {
+ pins = "gpio69", "gpio70";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci1_default: cci1-default-state {
+ pins = "gpio71", "gpio72";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci1_sleep: cci1-sleep-state {
+ pins = "gpio71", "gpio72";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci2_default: cci2-default-state {
+ pins = "gpio73", "gpio74";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci2_sleep: cci2-sleep-state {
+ pins = "gpio73", "gpio74";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci3_default: cci3-default-state {
+ pins = "gpio75", "gpio76";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci3_sleep: cci3-sleep-state {
+ pins = "gpio75", "gpio76";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
dp_hot_plug_det: dp-hot-plug-det-state {
pins = "gpio47";
function = "dp_hot";