From patchwork Thu Sep 28 15:15:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 146783 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6359:6f87:b0:13f:353d:d1ed with SMTP id tl7csp3561523rwb; Fri, 29 Sep 2023 14:24:43 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHx/zOgCfYB5olmxNlTFLG6lp0+XawJHgHWkgVPcKZivxujsINJhL+0cU4/CMPER9EWO5je X-Received: by 2002:a05:6870:2429:b0:1dd:7f3b:4f6f with SMTP id n41-20020a056870242900b001dd7f3b4f6fmr5413701oap.20.1696022683606; Fri, 29 Sep 2023 14:24:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696022683; cv=none; d=google.com; s=arc-20160816; b=PClGt1z90CAMjR3pj4QutGcpCOIG30X6cK62f/GjhyTPoKfQ9kdaADsOG+bhMuCE5+ 0ZvuLkBIWgbpJ7b72EqAqAAsDYIK7wI/JY6B7RaAaCGnAnegChAk7WCJfj9s8iBMKzko /4RomR1lwrte9PuqQZpVEn6OPGYBU45bznHrXMqiDmH4fbF8tHTnz4l1BHZGkoD8jS0Q eXXl/aRY7mN/tdC4oYerYCJQQsXVjd+kMrlPImcBYdDaHueJWpwRkIMO7bleQw+2FpDz JEmnuLQy4LZAj8bjU8+btYJBe9br17llyBWqYFlPhrTd54/H0HFDx+GIflkghQZlg3eG NghQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=RBXVmwb6jNT2iUShZk/ZgEGot9S1AER/3jhHyMGTE+c=; fh=Nrq3/ZyqAmcldX4TnYQJDytRSUiD1vJeQNniXh+eWjo=; b=rvCYtVB6+TGrGKgRThUCSpX7/xoCIBY7PBbL97Qlpp6Ob69hGoEc0Y8wR+ztCUgEPD cRxvYWUkeqcweTElpFy43EOafZMZNO8anYUU4sC+YfvycSKdxH08jSfUs+P78ndAnSxI oi9YXSusuW2SE7NDR/l5U99FYG9ZDHm8ENOyxnROg9On47dEZV0ftnhVfkFr3/t8PF/Z s2ziu1+Bf4gvprGnneS+NOwxy8hy4lIw/2J3w1TJPleGFWErVy+HD0C522gwcl7CENkD VUnrfcxinaONMbi6n2+QZw4BaflGW3Grn+8igQg+1+YJ4NbwavhwJ7lCkW6hHBJ1RjoR gjhA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b="uDLE/bll"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id 126-20020a630284000000b00565f611a1f8si20957819pgc.263.2023.09.29.14.24.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Sep 2023 14:24:43 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b="uDLE/bll"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id DE26D818F687; Thu, 28 Sep 2023 08:17:33 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232029AbjI1PRU (ORCPT + 21 others); Thu, 28 Sep 2023 11:17:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40318 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232011AbjI1PRM (ORCPT ); Thu, 28 Sep 2023 11:17:12 -0400 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4489410C4; Thu, 28 Sep 2023 08:17:01 -0700 (PDT) Received: from pps.filterd (m0369458.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 38SE1jJs007793; Thu, 28 Sep 2023 17:16:31 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=RBXVmwb6jNT2iUShZk/ZgEGot9S1AER/3jhHyMGTE+c=; b=uD LE/blludOOkCNvI579XO1bQevlIlwvuzI5xsJadyo4wm6LOU/89Q3h32iLjDpfZ8 EzAnEVXPb1mWQf57PFVhH5Pgt0LeGNBzTar0X4rloPAX3BKmlTCOqtQhUH39VG34 y9jlCvzL5Ab/K3ljqpnL4TqZp7hvSa9JaOAytw+A87wXo69ZChEehgsznEpme6tu Qz4Wj3Aal8TXlrGTtAVaBBE7rT+yeSoOf7Hk1XyTjc5Jx/CVx3aFctA4yrPX6tm8 gFsRA6cG9ycyWkbWKKODnZVp2v5cHsTWxTTlNJe9q/uh3P85H6CWcxIMurdED2cG IVuLf18GYyQC/y3sVq7A== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3ta9k0my07-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 28 Sep 2023 17:16:31 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id C5277100058; Thu, 28 Sep 2023 17:16:30 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id B714324553E; Thu, 28 Sep 2023 17:16:30 +0200 (CEST) Received: from localhost (10.201.21.249) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 28 Sep 2023 17:16:30 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier CC: , , , , Subject: [PATCH v3 06/12] net: ethernet: stmmac: stm32: update config management for phy wo cristal Date: Thu, 28 Sep 2023 17:15:06 +0200 Message-ID: <20230928151512.322016-7-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230928151512.322016-1-christophe.roullier@foss.st.com> References: <20230928151512.322016-1-christophe.roullier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.21.249] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-28_14,2023-09-28_02,2023-05-22_02 X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Thu, 28 Sep 2023 08:17:33 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778408681301572144 X-GMAIL-MSGID: 1778408681301572144 From: Christophe Roullier Some cleaning because some Ethernet PHY configs do not need to add st,ext-phyclk property Change print info message "No phy clock provided" only when debug Signed-off-by: Christophe Roullier --- .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 27 ++++++++++--------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c index a071dc6ffc95b..1210062f0832a 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c @@ -55,17 +55,17 @@ *| | | 25MHz | 50MHz | | * --------------------------------------------------------------------------- *| MII | - | eth-ck | n/a | n/a | - *| | | st,ext-phyclk | | | + *| | | | | | * --------------------------------------------------------------------------- *| GMII | - | eth-ck | n/a | n/a | - *| | | st,ext-phyclk | | | + *| | | | | | * --------------------------------------------------------------------------- *| RGMII | - | eth-ck | n/a | eth-ck | - *| | | st,ext-phyclk | | st,eth-clk-sel or| + *| | | | | st,eth-clk-sel or| *| | | | | st,ext-phyclk | * --------------------------------------------------------------------------- *| RMII | - | eth-ck | eth-ck | n/a | - *| | | st,ext-phyclk | st,eth-ref-clk-sel | | + *| | | | st,eth-ref-clk-sel | | *| | | | or st,ext-phyclk | | * --------------------------------------------------------------------------- * @@ -180,23 +180,22 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) dwmac->enable_eth_ck = false; switch (plat_dat->mac_interface) { case PHY_INTERFACE_MODE_MII: - if (clk_rate == ETH_CK_F_25M && dwmac->ext_phyclk) + if (clk_rate == ETH_CK_F_25M) dwmac->enable_eth_ck = true; val = dwmac->ops->pmcsetr.eth1_selmii; pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n"); break; case PHY_INTERFACE_MODE_GMII: val = SYSCFG_PMCR_ETH_SEL_GMII; - if (clk_rate == ETH_CK_F_25M && - (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) { + if (clk_rate == ETH_CK_F_25M) dwmac->enable_eth_ck = true; - val |= dwmac->ops->pmcsetr.eth1_clk_sel; - } pr_debug("SYSCFG init : PHY_INTERFACE_MODE_GMII\n"); break; case PHY_INTERFACE_MODE_RMII: val = dwmac->ops->pmcsetr.eth1_sel_rmii | dwmac->ops->pmcsetr.eth2_sel_rmii; - if ((clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_50M) && + if (clk_rate == ETH_CK_F_25M) + dwmac->enable_eth_ck = true; + if ((clk_rate == ETH_CK_F_50M) && (dwmac->eth_ref_clk_sel_reg || dwmac->ext_phyclk)) { dwmac->enable_eth_ck = true; val |= dwmac->ops->pmcsetr.eth1_ref_clk_sel; @@ -209,7 +208,9 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII_TXID: val = dwmac->ops->pmcsetr.eth1_sel_rgmii | dwmac->ops->pmcsetr.eth2_sel_rgmii; - if ((clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_125M) && + if (clk_rate == ETH_CK_F_25M) + dwmac->enable_eth_ck = true; + if ((clk_rate == ETH_CK_F_125M) && (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) { dwmac->enable_eth_ck = true; val |= dwmac->ops->pmcsetr.eth1_clk_sel; @@ -225,7 +226,7 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) } /* Need to update PMCCLRR (clear register) */ - regmap_write(dwmac->regmap, reg + dwmac->ops->syscfg_clr_off, + regmap_write(dwmac->regmap, dwmac->ops->syscfg_clr_off, dwmac->mode_mask); /* Update PMCSETR (set register) */ @@ -332,7 +333,7 @@ static int stm32mp1_parse_data(struct stm32_dwmac *dwmac, /* Get ETH_CLK clocks */ dwmac->clk_eth_ck = devm_clk_get(dev, "eth-ck"); if (IS_ERR(dwmac->clk_eth_ck)) { - dev_info(dev, "No phy clock provided...\n"); + dev_dbg(dev, "No phy clock provided...\n"); dwmac->clk_eth_ck = NULL; }