From patchwork Thu Sep 28 15:15:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 146257 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:cae8:0:b0:403:3b70:6f57 with SMTP id r8csp3525885vqu; Thu, 28 Sep 2023 11:51:10 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE6VuRNJPm4pdjzuCHqHMTQacDEVNuznldeIbJIXwZH3Lct1bM31wWnUqg7TgJ+E6/0Cpju X-Received: by 2002:a05:6a21:8190:b0:15e:ab6:6e24 with SMTP id pd16-20020a056a21819000b0015e0ab66e24mr1864599pzb.27.1695927069672; Thu, 28 Sep 2023 11:51:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695927069; cv=none; d=google.com; s=arc-20160816; b=aFWiWt3j/r8T0ZG03BAz2Kcu6sZUNwcxmyrCro1YfWzCd9N68culiLnuUA/wVykc2c 2ExEV9aYIzCJ1kQ2rjJGBm9yYYwmTViaWM22N51YnkhVP2hBTJkXD8gB1o0rfnZVb6ZL xZ9pB0L6lvsMXndG5k0ErWpxEq5U3sE1x2x+PEov5kAYmxKoVmlr9GKx75bv5iTWKi5P Xw3+idLGWLpszNIW/ANLiF5MwqxL10St35gAuW2mhriSmvgfPr9A5a7wcFuNm5sIkJzS leSFFJ9Nf++dISgcSPBGpMjsl4Mt77VdWmhiwHeoCsTw6oRIpgcoMNyeBJTETjLVLS3B t9dw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=em1iavzcmoXt7sbQ99esOEY41Vxo8iurL0awxGXDL90=; fh=Nrq3/ZyqAmcldX4TnYQJDytRSUiD1vJeQNniXh+eWjo=; b=LZzrI3tc//6DKoEu6Mtwl27SaxZ2WLGIuflQXASgGLB5R9S+uZ7ZuKnWpPLbUhJB+8 DzEiJ4CXYOyqymEMHY1JCUf9Yt2he93sUpEyzYEYK5UapKcCTyj6BP9ZeIqg+7Pgwr+R 6LCrhc4QtbcAKaWjWWNZJAsSk1jlNahH4eND0/9wfUF575kpMsGTkDYdg7hGaA0hd/6F syO8Lhj1njp5gLagxZ7g54J6tAwrn/9b8nTOwnGCW6trnXQgSuthGxoa11chm75Uxyhl EZuagg/G1UQ0BK1bxZDPL2jYoe839GVXwmnYJgWva/lTHbU5Cg1qmiHWZr6brC25msmz xMiA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=LIYMx9Yb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from agentk.vger.email (agentk.vger.email. [23.128.96.32]) by mx.google.com with ESMTPS id k18-20020a170902c41200b001bc8a9f5e52si22855967plk.135.2023.09.28.11.51.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 11:51:09 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) client-ip=23.128.96.32; Authentication-Results: mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=LIYMx9Yb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by agentk.vger.email (Postfix) with ESMTP id 2F87981F88F7; Thu, 28 Sep 2023 08:19:06 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at agentk.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231844AbjI1PS0 (ORCPT + 21 others); Thu, 28 Sep 2023 11:18:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57794 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231805AbjI1PSO (ORCPT ); Thu, 28 Sep 2023 11:18:14 -0400 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C8658CD8; Thu, 28 Sep 2023 08:18:07 -0700 (PDT) Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 38SEDLvj005075; Thu, 28 Sep 2023 17:17:46 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=em1iavzcmoXt7sbQ99esOEY41Vxo8iurL0awxGXDL90=; b=LI YMx9YbEeASjjOo8F+l3jxbkrnvwiOwWY50+A82rdVjVwVa8TKURlbjNGS0yBjyMg pN+YrfCTfISMRiTwApkdh3irxw4jcsdMbqWENaprxnWWM9iUBCQZndQz60ze3ay5 qXagQGbSthOao5TGDjlZGL/58rhINy3/3qcZuJfJr5UtF8fJrWjiPUmXLOMlHSzK JOwcEEPtg4dJgh3Q8ZinkckkJiPAFEoL69IhbqUg80OR/Gd/sr7RlfqG3hSkLDJf gNwLlKLvNQyJJigXvGK39HJKvtH6T99aDpbViF9I+z+e3TJ3f4Zos2UM1eRMk/VU +xiXo+a7c1fwuc0Jg+ag== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3taayhwhxa-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 28 Sep 2023 17:17:46 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 20FF9100058; Thu, 28 Sep 2023 17:17:46 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 170E724B887; Thu, 28 Sep 2023 17:17:46 +0200 (CEST) Received: from localhost (10.201.21.249) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 28 Sep 2023 17:17:43 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier CC: , , , , Subject: [PATCH v3 10/12] ARM: dts: stm32: add ethernet1/2 RMII pins for STM32MP13F-DK board Date: Thu, 28 Sep 2023 17:15:10 +0200 Message-ID: <20230928151512.322016-11-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230928151512.322016-1-christophe.roullier@foss.st.com> References: <20230928151512.322016-1-christophe.roullier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.21.249] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-28_14,2023-09-28_02,2023-05-22_02 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Thu, 28 Sep 2023 08:19:06 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778308422586722930 X-GMAIL-MSGID: 1778308422586722930 Those pins are used for Ethernet 1 and 2 on STM32MP13F-DK board. ethernet1: RMII with crystal. ethernet2: RMII without crystal. Add analog gpio pin configuration ("sleep") to manage power mode on stm32mp13. Signed-off-by: Christophe Roullier --- arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 71 +++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi index 27e0c3826789d..b2583df813af8 100644 --- a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi @@ -13,6 +13,77 @@ pins { }; }; + eth1_rmii_pins_a: eth1-rmii-0 { + pins1 { + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_TX_EN */ + , /* ETH_RMII_REF_CLK */ + , /* ETH_MDIO */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = , /* ETH_RMII_RXD0 */ + , /* ETH_RMII_RXD1 */ + ; /* ETH_RMII_CRS_DV */ + bias-disable; + }; + + }; + + eth1_rmii_sleep_pins_a: eth1-rmii-sleep-0 { + pins1 { + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_TX_EN */ + , /* ETH_RMII_REF_CLK */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RMII_RXD0 */ + , /* ETH_RMII_RXD1 */ + ; /* ETH_RMII_CRS_DV */ + }; + }; + + eth2_rmii_pins_a: eth2-rmii-0 { + pins1 { + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_ETHCK */ + , /* ETH_RMII_TX_EN */ + , /* ETH_MDIO */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = , /* ETH_RMII_RXD0 */ + , /* ETH_RMII_RXD1 */ + ; /* ETH_RMII_CRS_DV */ + bias-disable; + }; + }; + + eth2_rmii_sleep_pins_a: eth2-rmii-sleep-0 { + pins1 { + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_ETHCK */ + , /* ETH_RMII_TX_EN */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RMII_RXD0 */ + , /* ETH_RMII_RXD1 */ + ; /* ETH_RMII_CRS_DV */ + }; + }; + i2c1_pins_a: i2c1-0 { pins { pinmux = , /* I2C1_SCL */