Message ID | 20230928143644.208515-1-nicolas.ferre@microchip.com |
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State | New |
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[2620:137:e000::3:6]) by mx.google.com with ESMTPS id 125-20020a630083000000b005859af516b9si389786pga.647.2023.09.28.12.55.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 12:55:22 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) client-ip=2620:137:e000::3:6; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=sazsowTw; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id 2BA2C83A4790; Thu, 28 Sep 2023 07:37:58 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230517AbjI1Ohq (ORCPT <rfc822;pwkd43@gmail.com> + 21 others); Thu, 28 Sep 2023 10:37:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230201AbjI1Oho (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Thu, 28 Sep 2023 10:37:44 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 27F1B136; Thu, 28 Sep 2023 07:37:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1695911860; x=1727447860; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=VX9nwVrqBkZ7pbyV1snJDbtj8uP2ZRcb8DPHidThz1s=; b=sazsowTwNhvyoYy5NL/VSbFdomLdEM5yzLki8QVuvGUf8HCyIdHCxSOL 3MrUlu7ZLECvXxSbbekadsYrA5JpknOttmFhVRYl2ItN6jyNQiBst6A5O oJeyZvr2tVio0jh4sldsjA+VczMt6MKcxblUXsGwZGURTZEn8cyujImiV lXkoCSorXF3Dv4kIRZMgzixbxv/00pKxtGhS2BB3b8Kr2o/xnvMckqD5e 12CsxmMpJH+fTkxaPWk+P83AkTiKDC+3N18VEB/TzwrFhzbZ0sdXJTJVX 2nLqqw8tCRHLohTqIad3P8KArCLK5/FXefgwl60aaDr0EyBEuGo1w1iKQ A==; X-CSE-ConnectionGUID: Xa7eooHcQCaStKetqeRDsQ== X-CSE-MsgGUID: yGN/veqWQmCaCtwapdt2aQ== X-ThreatScanner-Verdict: Negative X-IronPort-AV: E=Sophos;i="6.03,184,1694761200"; d="scan'208";a="7359184" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 28 Sep 2023 07:37:40 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Thu, 28 Sep 2023 07:37:10 -0700 Received: from ROU-LL-M43238.home (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Thu, 28 Sep 2023 07:37:08 -0700 From: <nicolas.ferre@microchip.com> To: Claudiu Beznea <claudiu.beznea@tuxon.dev>, <linux-arm-kernel@lists.infradead.org> CC: Alexandre Belloni <alexandre.belloni@bootlin.com>, <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>, Tudor Ambarus <tudor.ambarus@linaro.org> Subject: [PATCH] ARM: dts: at91: sam9x60_curiosity: Add mandatory dt property for RTT Date: Thu, 28 Sep 2023 16:36:44 +0200 Message-ID: <20230928143644.208515-1-nicolas.ferre@microchip.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Thu, 28 Sep 2023 07:37:58 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778312462975098660 X-GMAIL-MSGID: 1778312462975098660 |
Series |
ARM: dts: at91: sam9x60_curiosity: Add mandatory dt property for RTT
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Commit Message
Nicolas Ferre
Sept. 28, 2023, 2:36 p.m. UTC
From: Tudor Ambarus <tudor.ambarus@linaro.org> atmel,rtt-rtc-time-reg is a mandatory property and encodes the GPBR register used to store the time base when the RTT is used as an RTC. Align the RTT with what's currently done for sam9x60ek and sama7g5ek, and enable it by default even if RTC is also enabled. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> [nicolas.ferre@microchip.com: adapt to newer kernel] Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> --- arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts | 4 ++++ 1 file changed, 4 insertions(+)
Comments
On 28.09.2023 17:36, nicolas.ferre@microchip.com wrote: > From: Tudor Ambarus <tudor.ambarus@linaro.org> > > atmel,rtt-rtc-time-reg is a mandatory property and encodes the GPBR > register used to store the time base when the RTT is used as an RTC. > Align the RTT with what's currently done for sam9x60ek and sama7g5ek, > and enable it by default even if RTC is also enabled. > > Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> > [nicolas.ferre@microchip.com: adapt to newer kernel] > Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> > --- > arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts > index cb86a3a170ce..83372c1f291b 100644 > --- a/arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts > +++ b/arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts > @@ -439,6 +439,10 @@ &pwm0 { > status = "okay"; > }; > > +&rtt { > + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; > +}; > + > &sdmmc0 { > bus-width = <4>; > pinctrl-names = "default";
On 28.09.2023 17:36, nicolas.ferre@microchip.com wrote: > From: Tudor Ambarus <tudor.ambarus@linaro.org> > > atmel,rtt-rtc-time-reg is a mandatory property and encodes the GPBR > register used to store the time base when the RTT is used as an RTC. > Align the RTT with what's currently done for sam9x60ek and sama7g5ek, > and enable it by default even if RTC is also enabled. > > Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> > [nicolas.ferre@microchip.com: adapt to newer kernel] > Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Applied to at91-dt, thanks!
diff --git a/arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts index cb86a3a170ce..83372c1f291b 100644 --- a/arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts +++ b/arch/arm/boot/dts/microchip/at91-sam9x60_curiosity.dts @@ -439,6 +439,10 @@ &pwm0 { status = "okay"; }; +&rtt { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; +}; + &sdmmc0 { bus-width = <4>; pinctrl-names = "default";