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[v2,3/9] dt-bindings: riscv: Add Zicond extension entry

Message ID	20230925133859.1735879-4-apatel@ventanamicro.com
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) client-ip=2620:137:e000::3:3; From: Anup Patel <apatel@ventanamicro.com> To: Paolo Bonzini <pbonzini@redhat.com>, Atish Patra <atishp@atishpatra.org>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Conor Dooley <conor@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Shuah Khan <shuah@kernel.org> Cc: Andrew Jones <ajones@ventanamicro.com>, Mayuresh Chitale <mchitale@ventanamicro.com>, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel <apatel@ventanamicro.com> Subject: [PATCH v2 3/9] dt-bindings: riscv: Add Zicond extension entry Date: Mon, 25 Sep 2023 19:08:53 +0530 Message-Id: <20230925133859.1735879-4-apatel@ventanamicro.com> In-Reply-To: <20230925133859.1735879-1-apatel@ventanamicro.com> References: <20230925133859.1735879-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	KVM RISC-V Conditional Operations \| [v2,0/9] KVM RISC-V Conditional Operations [v2,1/9] dt-bindings: riscv: Add XVentanaCondOps extension entry [v2,2/9] RISC-V: Detect XVentanaCondOps from ISA string [v2,3/9] dt-bindings: riscv: Add Zicond extension entry [v2,4/9] RISC-V: Detect Zicond from ISA string [v2,5/9] RISC-V: KVM: Allow XVentanaCondOps extension for Guest/VM [v2,6/9] RISC-V: KVM: Allow Zicond extension for Guest/VM [v2,7/9] KVM: riscv: selftests: Add senvcfg register to get-reg-list test [v2,8/9] KVM: riscv: selftests: Add smstateen registers to get-reg-list test [v2,9/9] KVM: riscv: selftests: Add condops extensions to get-reg-list test

Commit Message

Anup Patel Sept. 25, 2023, 1:38 p.m. UTC

  Add an entry for the Zicond extension to the riscv,isa-extensions property.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

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Patch

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index cad8ef68eca7..3f0b47686080 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -225,6 +225,12 @@  properties:
             ratified in the 20191213 version of the unprivileged ISA
             specification.
 
+        - const: zicond
+          description:
+            The standard Zicond extension for conditional arithmetic and
+            conditional-select/move operations as ratified in commit 95cf1f9
+            ("Add changes requested by Ved during signoff") of riscv-zicond.
+
         - const: zicsr
           description: |
             The standard Zicsr extension for control and status register