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Sat, 23 Sep 2023 16:34:43 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-clk@vger.kernel.org, openbmc@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , Daniel Lezcano , Thomas Gleixner , Philipp Zabel , Wim Van Sebroeck , Guenter Roeck , Christophe JAILLET , Conor Dooley , Krzysztof Kozlowski Subject: [PATCH v9 1/3] dt-bindings: clock: Add Nuvoton WPCM450 clock/reset controller Date: Sat, 23 Sep 2023 16:34:36 +0200 Message-Id: <20230923143438.1895461-2-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230923143438.1895461-1-j.neuschaefer@gmx.net> References: <20230923143438.1895461-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:mslaQFimglJP+UqzYug/aoohF1vHtd/u37CmOlAgx0oZtkTJ7uH yoijsWD8+rPUXCaOxysdEIPP8tgfkEb4SARqWdzM+C/MW9bZJgq8rHU5HcsLO9TB5IdLgAa fid36w/pNzakbjTNuXch7uMJtak5Fd1YsGPAtn4iI669XKY+TEDdpzxcnUu2qOjh9tZN4nF vUPyzIoXARk8Vn/PHkuGA== UI-OutboundReport: notjunk:1;M01:P0:5WCmLvF6sHY=;hSYyI2jgSuYsysimdRz4DL+S0Fd SZ23WUWdPDDoOqILnQIkZfCqE4p8pmYoGMfxuMFoqyFY5pFPJQm/00LgU2SVHyfmstPqGOO7E alAu6RpVxpTq3fW3BVktPW86Ye1vd4OmZJgtJSGkv5bK6tqWcGL2qyUgOzpvSYTnYCCDjNGN3 HtRLCu17Y+0fupQFOH8QJMRqZVtYrOAN2TxX4XzYYW+4IfoljnF+jC55qjpw5ttowW/e+7dPX 97xSwd5s2Mz4ti+prDjopUK/j4824rQMBnvKUwyJHO56NZFP9ku9hKRpEW6SKCVV0RDNR4CJy Kw5B3mgBXt8VPRYYFlUKtAnQGkU/jluD4q52xGx9F/kZC38Fey8RW0CHEXL/c0pMG1DsSGxtg GDdekCOIGVU14ZWy+evziD6/+G7CLzgIxI0NY7YV5rhQefg8Pis+wbR/YB+dU/mmLzT+Itsw1 V452AX+1XT5BWi0nBwK9+qbSHk6yrpWsWDD1MbA7ySnhobkPexsJkRZx5+G1H5y+l0lPI5D4d 5npCUinjoWvCwHwnW7m57rj2NTv3lEqf3GAGPRfmbkb+mfb8JBvepcaDW2kLjZvsiIoaI+wtY OcLKCkDbXb8YYoypcsizXt/g9Ra5jPDw3NE9VkBc4+XRNitDJcAxx1g2JvcS5lwGGdX3rVYd7 Ua/yd5CRtJ4yPvg8WiYOk6d6WrG0LTV1YKma16zee3bACs607cvl4TpkRhRsp5i+C7HUGSfVQ 8PkIwaYUkmWtNXEqpznzBGtzpoolGInzVbxVg+Ac/v2X+UC70rAbQAtDk8zQcJdzzHgd/dzYP 6D/cqkYsBVZ3uVzGhJnT1An70ONiMFF/c3nkS+Z4/bIV6MVsAYNgHsZ6P9u/WNaqanKoYojz+ xkj2H5d2KoM01Xhql1m8ConyTMZbKXuK6YigU4KP3iRTC4udA5lH9QApoC+6jvmCcVGA/eegF bZdi0bZP+msZI/q42sZzq5P0KH4= X-Spam-Status: No, score=3.0 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RCVD_IN_SBL_CSS, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Sat, 23 Sep 2023 07:35:52 -0700 (PDT) X-Spam-Level: ** X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777849213043109373 X-GMAIL-MSGID: 1777849213043109373 The Nuvoton WPCM450 SoC has a combined clock and reset controller. Add a devicetree binding for it, as well as definitions for the bit numbers used by it. Signed-off-by: Jonathan Neuschäfer Reviewed-by: Krzysztof Kozlowski --- v9: - Remove clock-output-names in example, because it's now unnecessary due to driver improvements v5-v8: - no changes v4: - https://lore.kernel.org/lkml/20220610072141.347795-4-j.neuschaefer@gmx.net/ - Add R-b tag v3: - Change clock-output-names and clock-names from "refclk" to "ref", suggested by Krzysztof Kozlowski v2: - https://lore.kernel.org/lkml/20220429172030.398011-5-j.neuschaefer@gmx.net/ - Various improvements, suggested by Krzysztof Kozlowski v1: - https://lore.kernel.org/lkml/20220422183012.444674-5-j.neuschaefer@gmx.net/ --- .../bindings/clock/nuvoton,wpcm450-clk.yaml | 65 ++++++++++++++++++ .../dt-bindings/clock/nuvoton,wpcm450-clk.h | 67 +++++++++++++++++++ 2 files changed, 132 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml create mode 100644 include/dt-bindings/clock/nuvoton,wpcm450-clk.h -- 2.40.1 diff --git a/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml new file mode 100644 index 0000000000000..93521cf68a040 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nuvoton,wpcm450-clk.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nuvoton,wpcm450-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton WPCM450 clock controller + +maintainers: + - Jonathan Neuschäfer + +description: + The clock controller of the Nuvoton WPCM450 SoC supplies clocks and resets to + the rest of the chip. + +properties: + compatible: + const: nuvoton,wpcm450-clk + + reg: + maxItems: 1 + + clocks: + items: + - description: Reference clock oscillator (should be 48 MHz) + + clock-names: + items: + - const: ref + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +examples: + - | + #include + #include + + refclk: clock-48mhz { + /* 48 MHz reference oscillator */ + compatible = "fixed-clock"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + + clk: clock-controller@b0000200 { + reg = <0xb0000200 0x100>; + compatible = "nuvoton,wpcm450-clk"; + clocks = <&refclk>; + clock-names = "ref"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/nuvoton,wpcm450-clk.h b/include/dt-bindings/clock/nuvoton,wpcm450-clk.h new file mode 100644 index 0000000000000..86e1c895921b7 --- /dev/null +++ b/include/dt-bindings/clock/nuvoton,wpcm450-clk.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H +#define _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H + +/* Clocks based on CLKEN bits */ +#define WPCM450_CLK_FIU 0 +#define WPCM450_CLK_XBUS 1 +#define WPCM450_CLK_KCS 2 +#define WPCM450_CLK_SHM 4 +#define WPCM450_CLK_USB1 5 +#define WPCM450_CLK_EMC0 6 +#define WPCM450_CLK_EMC1 7 +#define WPCM450_CLK_USB0 8 +#define WPCM450_CLK_PECI 9 +#define WPCM450_CLK_AES 10 +#define WPCM450_CLK_UART0 11 +#define WPCM450_CLK_UART1 12 +#define WPCM450_CLK_SMB2 13 +#define WPCM450_CLK_SMB3 14 +#define WPCM450_CLK_SMB4 15 +#define WPCM450_CLK_SMB5 16 +#define WPCM450_CLK_HUART 17 +#define WPCM450_CLK_PWM 18 +#define WPCM450_CLK_TIMER0 19 +#define WPCM450_CLK_TIMER1 20 +#define WPCM450_CLK_TIMER2 21 +#define WPCM450_CLK_TIMER3 22 +#define WPCM450_CLK_TIMER4 23 +#define WPCM450_CLK_MFT0 24 +#define WPCM450_CLK_MFT1 25 +#define WPCM450_CLK_WDT 26 +#define WPCM450_CLK_ADC 27 +#define WPCM450_CLK_SDIO 28 +#define WPCM450_CLK_SSPI 29 +#define WPCM450_CLK_SMB0 30 +#define WPCM450_CLK_SMB1 31 + +/* Other clocks */ +#define WPCM450_CLK_USBPHY 32 + +#define WPCM450_NUM_CLKS 33 + +/* Resets based on IPSRST bits */ +#define WPCM450_RESET_FIU 0 +#define WPCM450_RESET_EMC0 6 +#define WPCM450_RESET_EMC1 7 +#define WPCM450_RESET_USB0 8 +#define WPCM450_RESET_USB1 9 +#define WPCM450_RESET_AES_PECI 10 +#define WPCM450_RESET_UART 11 +#define WPCM450_RESET_MC 12 +#define WPCM450_RESET_SMB2 13 +#define WPCM450_RESET_SMB3 14 +#define WPCM450_RESET_SMB4 15 +#define WPCM450_RESET_SMB5 16 +#define WPCM450_RESET_PWM 18 +#define WPCM450_RESET_TIMER 19 +#define WPCM450_RESET_ADC 27 +#define WPCM450_RESET_SDIO 28 +#define WPCM450_RESET_SSPI 29 +#define WPCM450_RESET_SMB0 30 +#define WPCM450_RESET_SMB1 31 + +#define WPCM450_NUM_RESETS 32 + +#endif /* _DT_BINDINGS_CLOCK_NUVOTON_WPCM450_CLK_H */