diff mbox series

[v11,05/37] x86/trapnr: Add event type macros to <asm/trapnr.h>

Message ID 20230923094212.26520-6-xin3.li@intel.com
State New
Headers
Series x86: enable FRED for x86-64 |

Commit Message

Li, Xin3 Sept. 23, 2023, 9:41 a.m. UTC 
  Intel VT-x classifies events into eight different types, which is
inherited by FRED for event identification. As such, event type
becomes a common x86 concept, and should be defined in a common x86
header.

Add event type macros to <asm/trapnr.h>, and use it in <asm/vmx.h>.

Suggested-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Tested-by: Shan Kang <shan.kang@intel.com>
Signed-off-by: Xin Li <xin3.li@intel.com>
---

Changes since v10:
* A few comment fixes and improvements (Andrew Cooper).
---
 arch/x86/include/asm/trapnr.h | 12 ++++++++++++
 arch/x86/include/asm/vmx.h    | 17 +++++++++--------
 2 files changed, 21 insertions(+), 8 deletions(-)

Comments

Nikolay Borisov Sept. 26, 2023, 8:10 a.m. UTC | #1 
On 23.09.23 г. 12:41 ч., Xin Li wrote:
> Intel VT-x classifies events into eight different types, which is
> inherited by FRED for event identification. As such, event type
> becomes a common x86 concept, and should be defined in a common x86
> header.
> 
> Add event type macros to <asm/trapnr.h>, and use it in <asm/vmx.h>.
> 
> Suggested-by: H. Peter Anvin (Intel) <hpa@zytor.com>
> Tested-by: Shan Kang <shan.kang@intel.com>
> Signed-off-by: Xin Li <xin3.li@intel.com>
> ---
> 
> Changes since v10:
> * A few comment fixes and improvements (Andrew Cooper).
> ---
>   arch/x86/include/asm/trapnr.h | 12 ++++++++++++
>   arch/x86/include/asm/vmx.h    | 17 +++++++++--------
>   2 files changed, 21 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/x86/include/asm/trapnr.h b/arch/x86/include/asm/trapnr.h
> index f5d2325aa0b7..8d1154cdf787 100644
> --- a/arch/x86/include/asm/trapnr.h
> +++ b/arch/x86/include/asm/trapnr.h
> @@ -2,6 +2,18 @@
>   #ifndef _ASM_X86_TRAPNR_H
>   #define _ASM_X86_TRAPNR_H
>   
> +/*
> + * Event type codes used by FRED, Intel VT-x and AMD SVM
> + */
> +#define EVENT_TYPE_EXTINT	0	// External interrupt
> +#define EVENT_TYPE_RESERVED	1
> +#define EVENT_TYPE_NMI		2	// NMI
> +#define EVENT_TYPE_HWEXC	3	// Hardware originated traps, exceptions
> +#define EVENT_TYPE_SWINT	4	// INT n
> +#define EVENT_TYPE_PRIV_SWEXC	5	// INT1
> +#define EVENT_TYPE_SWEXC	6	// INTO, INT3

nit: This turned into INTO (Oh) rather than INT0( zero) in v11

<nit>
Andrew Cooper Sept. 26, 2023, 9:26 a.m. UTC | #2 
On 26/09/2023 9:10 am, Nikolay Borisov wrote:
> On 23.09.23 г. 12:41 ч., Xin Li wrote:
>> diff --git a/arch/x86/include/asm/trapnr.h
>> b/arch/x86/include/asm/trapnr.h
>> index f5d2325aa0b7..8d1154cdf787 100644
>> --- a/arch/x86/include/asm/trapnr.h
>> +++ b/arch/x86/include/asm/trapnr.h
>> @@ -2,6 +2,18 @@
>>   #ifndef _ASM_X86_TRAPNR_H
>>   #define _ASM_X86_TRAPNR_H
>>   +/*
>> + * Event type codes used by FRED, Intel VT-x and AMD SVM
>> + */
>> +#define EVENT_TYPE_EXTINT    0    // External interrupt
>> +#define EVENT_TYPE_RESERVED    1
>> +#define EVENT_TYPE_NMI        2    // NMI
>> +#define EVENT_TYPE_HWEXC    3    // Hardware originated traps,
>> exceptions
>> +#define EVENT_TYPE_SWINT    4    // INT n
>> +#define EVENT_TYPE_PRIV_SWEXC    5    // INT1
>> +#define EVENT_TYPE_SWEXC    6    // INTO, INT3
>
> nit: This turned into INTO (Oh) rather than INT0( zero) in v11

Yes, v11 corrected a bug in v10.

The INTO instruction is "INT on Overflow".  No zero involved.

INT3 is thusly named because it generates vector 3.  Similarly for INT1
although it had the unofficial name ICEBP long before INT1 got documented.

If INTO were to have a number, it would need to be 4, but it's behaviour
is conditional on the overflow flag, unlike INT3/1 which are
unconditional exceptions.

~Andrew
Li, Xin3 Sept. 27, 2023, 5:15 a.m. UTC | #3 
> >> +EVENT_TYPE_PRIV_SWEXC    5    // INT1 #define EVENT_TYPE_SWEXC    6
> >> +// INTO, INT3
> >
> > nit: This turned into INTO (Oh) rather than INT0( zero) in v11
> 
> Yes, v11 corrected a bug in v10.
> 
> The INTO instruction is "INT on Overflow".  No zero involved.
> 
> INT3 is thusly named because it generates vector 3.  Similarly for INT1 although it
> had the unofficial name ICEBP long before INT1 got documented.
> 
> If INTO were to have a number, it would need to be 4, but it's behaviour is
> conditional on the overflow flag, unlike INT3/1 which are unconditional
> exceptions.

live x86 SDM!
H. Peter Anvin Sept. 27, 2023, 2:51 p.m. UTC | #4 
On September 26, 2023 1:10:51 AM PDT, Nikolay Borisov <nik.borisov@suse.com> wrote:
>
>
>On 23.09.23 г. 12:41 ч., Xin Li wrote:
>> Intel VT-x classifies events into eight different types, which is
>> inherited by FRED for event identification. As such, event type
>> becomes a common x86 concept, and should be defined in a common x86
>> header.
>> 
>> Add event type macros to <asm/trapnr.h>, and use it in <asm/vmx.h>.
>> 
>> Suggested-by: H. Peter Anvin (Intel) <hpa@zytor.com>
>> Tested-by: Shan Kang <shan.kang@intel.com>
>> Signed-off-by: Xin Li <xin3.li@intel.com>
>> ---
>> 
>> Changes since v10:
>> * A few comment fixes and improvements (Andrew Cooper).
>> ---
>>   arch/x86/include/asm/trapnr.h | 12 ++++++++++++
>>   arch/x86/include/asm/vmx.h    | 17 +++++++++--------
>>   2 files changed, 21 insertions(+), 8 deletions(-)
>> 
>> diff --git a/arch/x86/include/asm/trapnr.h b/arch/x86/include/asm/trapnr.h
>> index f5d2325aa0b7..8d1154cdf787 100644
>> --- a/arch/x86/include/asm/trapnr.h
>> +++ b/arch/x86/include/asm/trapnr.h
>> @@ -2,6 +2,18 @@
>>   #ifndef _ASM_X86_TRAPNR_H
>>   #define _ASM_X86_TRAPNR_H
>>   +/*
>> + * Event type codes used by FRED, Intel VT-x and AMD SVM
>> + */
>> +#define EVENT_TYPE_EXTINT	0	// External interrupt
>> +#define EVENT_TYPE_RESERVED	1
>> +#define EVENT_TYPE_NMI		2	// NMI
>> +#define EVENT_TYPE_HWEXC	3	// Hardware originated traps, exceptions
>> +#define EVENT_TYPE_SWINT	4	// INT n
>> +#define EVENT_TYPE_PRIV_SWEXC	5	// INT1
>> +#define EVENT_TYPE_SWEXC	6	// INTO, INT3
>
>nit: This turned into INTO (Oh) rather than INT0( zero) in v11
>
><nit>

INTO (letter) is correct.
diff mbox series

Patch

diff --git a/arch/x86/include/asm/trapnr.h b/arch/x86/include/asm/trapnr.h
index f5d2325aa0b7..8d1154cdf787 100644
--- a/arch/x86/include/asm/trapnr.h
+++ b/arch/x86/include/asm/trapnr.h
@@ -2,6 +2,18 @@ 
 #ifndef _ASM_X86_TRAPNR_H
 #define _ASM_X86_TRAPNR_H
 
+/*
+ * Event type codes used by FRED, Intel VT-x and AMD SVM
+ */
+#define EVENT_TYPE_EXTINT	0	// External interrupt
+#define EVENT_TYPE_RESERVED	1
+#define EVENT_TYPE_NMI		2	// NMI
+#define EVENT_TYPE_HWEXC	3	// Hardware originated traps, exceptions
+#define EVENT_TYPE_SWINT	4	// INT n
+#define EVENT_TYPE_PRIV_SWEXC	5	// INT1
+#define EVENT_TYPE_SWEXC	6	// INTO, INT3
+#define EVENT_TYPE_OTHER	7	// FRED SYSCALL/SYSENTER, VT-x MTF
+
 /* Interrupts/Exceptions */
 
 #define X86_TRAP_DE		 0	/* Divide-by-zero */
diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
index 0e73616b82f3..4dba17363008 100644
--- a/arch/x86/include/asm/vmx.h
+++ b/arch/x86/include/asm/vmx.h
@@ -17,6 +17,7 @@ 
 #include <linux/types.h>
 
 #include <uapi/asm/vmx.h>
+#include <asm/trapnr.h>
 #include <asm/vmxfeatures.h>
 
 #define VMCS_CONTROL_BIT(x)	BIT(VMX_FEATURE_##x & 0x1f)
@@ -374,14 +375,14 @@  enum vmcs_field {
 #define VECTORING_INFO_DELIVER_CODE_MASK    	INTR_INFO_DELIVER_CODE_MASK
 #define VECTORING_INFO_VALID_MASK       	INTR_INFO_VALID_MASK
 
-#define INTR_TYPE_EXT_INTR              (0 << 8) /* external interrupt */
-#define INTR_TYPE_RESERVED              (1 << 8) /* reserved */
-#define INTR_TYPE_NMI_INTR		(2 << 8) /* NMI */
-#define INTR_TYPE_HARD_EXCEPTION	(3 << 8) /* processor exception */
-#define INTR_TYPE_SOFT_INTR             (4 << 8) /* software interrupt */
-#define INTR_TYPE_PRIV_SW_EXCEPTION	(5 << 8) /* ICE breakpoint - undocumented */
-#define INTR_TYPE_SOFT_EXCEPTION	(6 << 8) /* software exception */
-#define INTR_TYPE_OTHER_EVENT           (7 << 8) /* other event */
+#define INTR_TYPE_EXT_INTR		(EVENT_TYPE_EXTINT << 8)	/* external interrupt */
+#define INTR_TYPE_RESERVED		(EVENT_TYPE_RESERVED << 8)	/* reserved */
+#define INTR_TYPE_NMI_INTR		(EVENT_TYPE_NMI << 8)		/* NMI */
+#define INTR_TYPE_HARD_EXCEPTION	(EVENT_TYPE_HWEXC << 8)		/* processor exception */
+#define INTR_TYPE_SOFT_INTR		(EVENT_TYPE_SWINT << 8)		/* software interrupt */
+#define INTR_TYPE_PRIV_SW_EXCEPTION	(EVENT_TYPE_PRIV_SWEXC << 8)	/* ICE breakpoint */
+#define INTR_TYPE_SOFT_EXCEPTION	(EVENT_TYPE_SWEXC << 8)		/* software exception */
+#define INTR_TYPE_OTHER_EVENT		(EVENT_TYPE_OTHER << 8)		/* other event */
 
 /* GUEST_INTERRUPTIBILITY_INFO flags. */
 #define GUEST_INTR_STATE_STI		0x00000001