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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier CC: , , , , Subject: [PATCH 6/7] ARM: dts: stm32: add ethernet1 and ethernet2 for STM32MP135F-DK board Date: Thu, 21 Sep 2023 17:06:21 +0200 Message-ID: <20230921150622.599232-7-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230921150622.599232-1-christophe.roullier@foss.st.com> References: <20230921150622.599232-1-christophe.roullier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.21.249] X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-21_13,2023-09-21_01,2023-05-22_02 X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Thu, 21 Sep 2023 13:48:52 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777689049913941084 X-GMAIL-MSGID: 1777689049913941084 Add dual Ethernet: -Ethernet1: RMII with crystal -Ethernet2: RMII without crystal With Ethernet1, we can performed WoL from PHY instead of GMAC point of view. (in this case IRQ for WoL is managed as wakeup pin and configured in OS secure). Signed-off-by: Christophe Roullier --- arch/arm/boot/dts/st/stm32mp135f-dk.dts | 48 +++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts index eea740d097c7..1316cc16f8dd 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -19,6 +19,8 @@ / { compatible = "st,stm32mp135f-dk", "st,stm32mp135"; aliases { + ethernet0 = ðernet1; + ethernet1 = ðernet2; serial0 = &uart4; serial1 = &usart1; serial2 = &uart8; @@ -93,6 +95,52 @@ channel@12 { }; }; +ðernet1 { + status = "okay"; + pinctrl-0 = <ð1_rmii_pins_a>; + pinctrl-1 = <ð1_rmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + max-speed = <100>; + phy-handle = <&phy0_eth1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy0_eth1: ethernet-phy@0 { + compatible = "ethernet-phy-id0007.c131"; + reset-gpios = <&mcp23017 9 GPIO_ACTIVE_LOW>; + reg = <0>; + wakeup-source; + }; + }; +}; + +ðernet2 { + status = "okay"; + pinctrl-0 = <ð2_rmii_pins_a>; + pinctrl-1 = <ð2_rmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + max-speed = <100>; + phy-handle = <&phy0_eth2>; + st,ext-phyclk; + phy-supply = <&scmi_v3v3_sw>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0_eth2: ethernet-phy@0 { + compatible = "ethernet-phy-id0007.c131"; + reset-gpios = <&mcp23017 10 GPIO_ACTIVE_LOW>; + reg = <0>; + }; + }; +}; + &i2c1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c1_pins_a>;