diff mbox series

riscv/mm: Fix the comment for swap pte format

Message ID 20230921141652.2657054-1-xiao.w.wang@intel.com
State New
Headers
Series riscv/mm: Fix the comment for swap pte format |

Commit Message

Wang, Xiao W Sept. 21, 2023, 2:16 p.m. UTC 
  Swap type takes bits 7-11 and swap offset should start from bit 12.

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
---
 arch/riscv/include/asm/pgtable.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

patchwork-bot+linux-riscv@kernel.org Oct. 27, 2023, 1:20 p.m. UTC | #1 
Hello:

This patch was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:

On Thu, 21 Sep 2023 22:16:52 +0800 you wrote:
> Swap type takes bits 7-11 and swap offset should start from bit 12.
> 
> Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
> ---
>  arch/riscv/include/asm/pgtable.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Here is the summary with links:
  - riscv/mm: Fix the comment for swap pte format
    https://git.kernel.org/riscv/c/9a2834e91d3d

You are awesome, thank you!
diff mbox series

Patch

diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index e05b5dc1f0cb..e94a2998e81e 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -812,7 +812,7 @@  extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
  *	bit            5:	_PAGE_PROT_NONE (zero)
  *	bit            6:	exclusive marker
  *	bits      7 to 11:	swap type
- *	bits 11 to XLEN-1:	swap offset
+ *	bits 12 to XLEN-1:	swap offset
  */
 #define __SWP_TYPE_SHIFT	7
 #define __SWP_TYPE_BITS		5