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[23.128.96.32]) by mx.google.com with ESMTPS id x1-20020a17090ab00100b0026d40e6a819si4398107pjq.157.2023.09.21.14.52.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 14:52:46 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) client-ip=23.128.96.32; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=AQ2vavD7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by agentk.vger.email (Postfix) with ESMTP id B52B5808E569; Thu, 21 Sep 2023 10:30:26 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at agentk.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230024AbjIUR3h (ORCPT + 29 others); Thu, 21 Sep 2023 13:29:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55146 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230340AbjIUR2x (ORCPT ); Thu, 21 Sep 2023 13:28:53 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD06651F78; Thu, 21 Sep 2023 10:17:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695316627; x=1726852627; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=R6y5ULZ42+b9n+Td0nzhf02tFYyolYBgBUdtJDkDQwc=; b=AQ2vavD7J3BjyQbxfpKodl0gLS0KngsreL+wI3xurF8H1hjSpAEwApc9 E+bX2IbP6GI+BYUxgMCrj6iKrSnEnCa3MlI8LVR19//PogXHqte7fSgps OeNug+XzAeIO0ZV0DjrM19o6Ja2chCyTXqidv7tjoV0TrdFU5qXupTTUi le0L1KOjoYhhR908RzQtjDl1+fRHNpbmrunFcze2iSjIuEm1Pt/PPAIAP cBP8+a9ydKg0AHW8Zd6GWN+mHlmd+/3g0LA4vurmz4aa4QhG5WnLMWZ8e s21MdqOUodlW+cktJMDrHptVfReXETyNKu0XWuFvwyHREXrb0mmQiVu7L Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10839"; a="444608167" X-IronPort-AV: E=Sophos;i="6.03,165,1694761200"; d="scan'208";a="444608167" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2023 05:20:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10839"; a="862441720" X-IronPort-AV: E=Sophos;i="6.03,165,1694761200"; d="scan'208";a="862441720" Received: from yongliang-ubuntu20-ilbpg12.png.intel.com ([10.88.229.33]) by fmsmga002.fm.intel.com with ESMTP; 21 Sep 2023 05:20:26 -0700 From: Choong Yong Liang To: Rajneesh Bhardwaj , David E Box , Hans de Goede , Mark Gross , Jose Abreu , Andrew Lunn , Heiner Kallweit , Russell King , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , =?utf-8?q?Marek_Beh=C3=BAn?= , Jean Delvare , Guenter Roeck , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Richard Cochran , Philipp Zabel , Alexei Starovoitov , Daniel Borkmann , Jesper Dangaard Brouer , John Fastabend , Wong Vee Khee , Jon Hunter , Jesse Brandeburg , Revanth Kumar Uppala , Shenwei Wang , Andrey Konovalov , Jochen Henneberg Cc: David E Box , Andrew Halaney , Simon Horman , Bartosz Golaszewski , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, platform-driver-x86@vger.kernel.org, linux-hwmon@vger.kernel.org, bpf@vger.kernel.org, Voon Wei Feng , Tan Tee Min , Michael Sit Wei Hong , Lai Peter Jun Ann Subject: [PATCH net-next v3 1/5] arch: x86: Add IPC mailbox accessor function and add SoC register access Date: Thu, 21 Sep 2023 20:19:42 +0800 Message-Id: <20230921121946.3025771-2-yong.liang.choong@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230921121946.3025771-1-yong.liang.choong@linux.intel.com> References: <20230921121946.3025771-1-yong.liang.choong@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Thu, 21 Sep 2023 10:30:26 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777685670430777185 X-GMAIL-MSGID: 1777685670430777185 From: "David E. Box" - Exports intel_pmc_ipc() for host access to the PMC IPC mailbox - Add support to use IPC command allows host to access SoC registers through PMC firmware that are otherwise inaccessible to the host due to security policies. Signed-off-by: David E. Box Signed-off-by: Chao Qin Signed-off-by: Choong Yong Liang --- MAINTAINERS | 2 + arch/x86/Kconfig | 9 +++ arch/x86/platform/intel/Makefile | 1 + arch/x86/platform/intel/pmc_ipc.c | 75 +++++++++++++++++++ .../linux/platform_data/x86/intel_pmc_ipc.h | 34 +++++++++ 5 files changed, 121 insertions(+) create mode 100644 arch/x86/platform/intel/pmc_ipc.c create mode 100644 include/linux/platform_data/x86/intel_pmc_ipc.h diff --git a/MAINTAINERS b/MAINTAINERS index 3dde038545d8..f608668fdfa6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10730,8 +10730,10 @@ M: Rajneesh Bhardwaj M: David E Box L: platform-driver-x86@vger.kernel.org S: Maintained +F: arch/x86/platform/intel/pmc_ipc.c F: Documentation/ABI/testing/sysfs-platform-intel-pmc F: drivers/platform/x86/intel/pmc/ +F: linux/platform_data/x86/intel_pmc_ipc.h INTEL PMIC GPIO DRIVERS M: Andy Shevchenko diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 982b777eadc7..31fc8ece2b46 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -666,6 +666,15 @@ config X86_AMD_PLATFORM_DEVICE I2C and UART depend on COMMON_CLK to set clock. GPIO driver is implemented under PINCTRL subsystem. +config INTEL_PMC_IPC + tristate "Intel Core SoC Power Management Controller IPC mailbox" + depends on ACPI + help + This option enables sideband register access support for Intel SoC + power management controller IPC mailbox. + + If you don't require the option or are in doubt, say N. + config IOSF_MBI tristate "Intel SoC IOSF Sideband support for SoC platforms" depends on PCI diff --git a/arch/x86/platform/intel/Makefile b/arch/x86/platform/intel/Makefile index dbee3b00f9d0..470fc68de6ba 100644 --- a/arch/x86/platform/intel/Makefile +++ b/arch/x86/platform/intel/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_IOSF_MBI) += iosf_mbi.o +obj-$(CONFIG_INTEL_PMC_IPC) += pmc_ipc.o \ No newline at end of file diff --git a/arch/x86/platform/intel/pmc_ipc.c b/arch/x86/platform/intel/pmc_ipc.c new file mode 100644 index 000000000000..a96234982710 --- /dev/null +++ b/arch/x86/platform/intel/pmc_ipc.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Intel Core SoC Power Management Controller IPC mailbox + * + * Copyright (c) 2023, Intel Corporation. + * All Rights Reserved. + * + * Authors: Choong Yong Liang + * David E. Box + */ +#include +#include +#include + +#define PMC_IPCS_PARAM_COUNT 7 + +int intel_pmc_ipc(struct pmc_ipc_cmd *ipc_cmd, u32 *rbuf) +{ + struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; + union acpi_object params[PMC_IPCS_PARAM_COUNT] = { + {.type = ACPI_TYPE_INTEGER,}, + {.type = ACPI_TYPE_INTEGER,}, + {.type = ACPI_TYPE_INTEGER,}, + {.type = ACPI_TYPE_INTEGER,}, + {.type = ACPI_TYPE_INTEGER,}, + {.type = ACPI_TYPE_INTEGER,}, + {.type = ACPI_TYPE_INTEGER,}, + }; + struct acpi_object_list arg_list = { PMC_IPCS_PARAM_COUNT, params }; + union acpi_object *obj; + int status; + + if (!ipc_cmd || !rbuf) + return -EINVAL; + + /* + * 0: IPC Command + * 1: IPC Sub Command + * 2: Size + * 3-6: Write Buffer for offset + */ + params[0].integer.value = ipc_cmd->cmd; + params[1].integer.value = ipc_cmd->sub_cmd; + params[2].integer.value = ipc_cmd->size; + params[3].integer.value = ipc_cmd->wbuf[0]; + params[4].integer.value = ipc_cmd->wbuf[1]; + params[5].integer.value = ipc_cmd->wbuf[2]; + params[6].integer.value = ipc_cmd->wbuf[3]; + + status = acpi_evaluate_object(NULL, "\\IPCS", &arg_list, &buffer); + if (ACPI_FAILURE(status)) + return -ENODEV; + + obj = buffer.pointer; + /* Check if the number of elements in package is 5 */ + if (obj && obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 5) { + const union acpi_object *objs = obj->package.elements; + + if ((u8)objs[0].integer.value != 0) + return -EINVAL; + + rbuf[0] = objs[1].integer.value; + rbuf[1] = objs[2].integer.value; + rbuf[2] = objs[3].integer.value; + rbuf[3] = objs[4].integer.value; + } else { + return -EINVAL; + } + + return 0; +} +EXPORT_SYMBOL(intel_pmc_ipc); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Intel PMC IPC Mailbox accessor"); diff --git a/include/linux/platform_data/x86/intel_pmc_ipc.h b/include/linux/platform_data/x86/intel_pmc_ipc.h new file mode 100644 index 000000000000..25ba57b8a7ea --- /dev/null +++ b/include/linux/platform_data/x86/intel_pmc_ipc.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Intel Core SoC Power Management Controller Header File + * + * Copyright (c) 2023, Intel Corporation. + * All Rights Reserved. + * + * Authors: Choong Yong Liang + * David E. Box + */ +#ifndef INTEL_PMC_IPC_H +#define INTEL_PMC_IPC_H + +#define IPC_SOC_REGISTER_ACCESS 0xAA +#define IPC_SOC_SUB_CMD_READ 0x00 +#define IPC_SOC_SUB_CMD_WRITE 0x01 + +struct pmc_ipc_cmd { + u32 cmd; + u32 sub_cmd; + u32 size; + u32 wbuf[4]; +}; + +/** + * intel_pmc_core_ipc() - PMC IPC Mailbox accessor + * @ipc_cmd: struct pmc_ipc_cmd prepared with input to send + * @rbuf: Allocated u32[4] array for returned IPC data + * + * Return: 0 on success. Non-zero on mailbox error + */ +int intel_pmc_ipc(struct pmc_ipc_cmd *ipc_cmd, u32 *rbuf); + +#endif /* INTEL_PMC_IPC_H */