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[2620:137:e000::3:3]) by mx.google.com with ESMTPS id k34-20020a17090a3ea500b00262ff3a4545si1713320pjc.169.2023.09.20.08.44.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 08:44:04 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) client-ip=2620:137:e000::3:3; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=OhPcdnxL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 35D228295BC3; Wed, 20 Sep 2023 02:24:52 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234081AbjITJYf (ORCPT + 26 others); Wed, 20 Sep 2023 05:24:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57642 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234011AbjITJYZ (ORCPT ); Wed, 20 Sep 2023 05:24:25 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73FC5191 for ; Wed, 20 Sep 2023 02:23:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695201827; x=1726737827; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fPbsFBLao1m6KO+ew1b44zTXvTcP/hWch9xcabu50YM=; b=OhPcdnxL1idRpEaftrk1+UlmB6q6HPZ6NJsRTtTq3lG0dEWEnmpNZn6B 5MstEzb+9IGFwsDR1OoDU67keaWRNPG3Tit6EgRqRqnGh1CDENUmSxMie FAegvyCCQ6Kpo0nGw6DiI1Kt1+W6/SukNd1Ysq2vfL7jdfrLxFTDBOrBO 94HXNFFUQkYwC3soUk1WOZ1A/93BFnb8tVHrOYgA+J+C2scb2pGrm/Jdm 95sdlBJmIKSEy26eNTGTykvy713nQzZv4NfPs3LZcVZDsUsLnW29cvgdM q0++/XR9t1W9TWe8nT20oqMNJY9BQ/7bh7g+7eHTxzeOKd0dnUyDm6Anu Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="444267597" X-IronPort-AV: E=Sophos;i="6.02,161,1688454000"; d="scan'208";a="444267597" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2023 02:23:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="781625271" X-IronPort-AV: E=Sophos;i="6.02,161,1688454000"; d="scan'208";a="781625271" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Sep 2023 02:23:44 -0700 From: Alexander Usyskin To: Greg Kroah-Hartman , Lucas De Marchi , Daniele Ceraolo Spurio , Rodrigo Vivi Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-xe@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/4] drm/xe/gsc: add HECI2 register offsets Date: Wed, 20 Sep 2023 12:19:20 +0300 Message-Id: <20230920091923.1573873-2-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230920091923.1573873-1-alexander.usyskin@intel.com> References: <20230920091923.1573873-1-alexander.usyskin@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Wed, 20 Sep 2023 02:24:52 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777571876851362020 X-GMAIL-MSGID: 1777571876851362020 From: Vitaly Lubart Add HECI2 register offsets for DG1 and DG2 to regs/xe_regs.h Reviewed-by: Rodrigo Vivi Signed-off-by: Vitaly Lubart Signed-off-by: Alexander Usyskin --- drivers/gpu/drm/xe/regs/xe_regs.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h index 39d7b0740bf0..4cbc3062cb9a 100644 --- a/drivers/gpu/drm/xe/regs/xe_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_regs.h @@ -33,6 +33,10 @@ #define XEHPC_BCS6_RING_BASE 0x3ea000 #define XEHPC_BCS7_RING_BASE 0x3ec000 #define XEHPC_BCS8_RING_BASE 0x3ee000 + +#define DG1_GSC_HECI2_BASE 0x00259000 +#define DG2_GSC_HECI2_BASE 0x00374000 + #define GSCCS_RING_BASE 0x11a000 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) #define GT_CONTEXT_SWITCH_INTERRUPT REG_BIT(8)