diff mbox series

[2/2] arm64: dts: marvell: eDPU: add support for version with external switch

Message ID 20230914094550.1519097-2-robert.marko@sartura.hr
State New
Headers
Series [1/2] arm64: dts: marvell: uDPU: rename the SFP GPIO properties |

Commit Message

Robert Marko Sept. 14, 2023, 9:45 a.m. UTC 
  New revision of eDPU uses an Marvell MV88E6361 switch to connect the SFP
cage and G.hn IC instead of connecting them directly to the ethernet
controllers.

U-Boot will enable the switch node and disable the unused ethernet
controller.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
 .../boot/dts/marvell/armada-3720-eDPU.dts     | 47 +++++++++++++++++++
 1 file changed, 47 insertions(+)

Comments

Andrew Lunn Sept. 14, 2023, 12:51 p.m. UTC | #1 
> +&mdio {
> +	status = "disabled";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&smi_pins>;
> +
> +	/* Actual device is MV88E6361 */
> +	switch: switch@0 {
> +		compatible = "marvell,mv88e6190";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		reg = <0>;
> +		status = "disabled";
> +
> +		ports {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			port@0 {
> +				reg = <0>;
> +				label = "cpu";
> +				phy-mode = "2500base-x";
> +				managed = "in-band-status";
> +				ethernet = <&eth0>;
> +			};
> +

So ports 1 through 7 are completely unused? 

> +			port@9 {
> +				reg = <9>;
> +				label = "downlink";
> +				phy-mode = "2500base-x";
> +				managed = "in-band-status";
> +			};

	Andrew
Gregory CLEMENT Sept. 20, 2023, 9:57 a.m. UTC | #2 
Robert Marko <robert.marko@sartura.hr> writes:

> New revision of eDPU uses an Marvell MV88E6361 switch to connect the SFP
> cage and G.hn IC instead of connecting them directly to the ethernet
> controllers.
>
> U-Boot will enable the switch node and disable the unused ethernet
> controller.
>


Applied on mvebu/dt64

Thanks,

Gregory

> Signed-off-by: Robert Marko <robert.marko@sartura.hr>
> ---
>  .../boot/dts/marvell/armada-3720-eDPU.dts     | 47 +++++++++++++++++++
>  1 file changed, 47 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts b/arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts
> index 57fc698e55d0..d6d37a1f6f38 100644
> --- a/arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts
> +++ b/arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts
> @@ -12,3 +12,50 @@ / {
>  &eth0 {
>  	phy-mode = "2500base-x";
>  };
> +
> +/*
> + * External MV88E6361 switch is only available on v2 of the board.
> + * U-Boot will enable the MDIO bus and switch nodes.
> + */
> +&mdio {
> +	status = "disabled";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&smi_pins>;
> +
> +	/* Actual device is MV88E6361 */
> +	switch: switch@0 {
> +		compatible = "marvell,mv88e6190";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		reg = <0>;
> +		status = "disabled";
> +
> +		ports {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			port@0 {
> +				reg = <0>;
> +				label = "cpu";
> +				phy-mode = "2500base-x";
> +				managed = "in-band-status";
> +				ethernet = <&eth0>;
> +			};
> +
> +			port@9 {
> +				reg = <9>;
> +				label = "downlink";
> +				phy-mode = "2500base-x";
> +				managed = "in-band-status";
> +			};
> +
> +			port@a {
> +				reg = <10>;
> +				label = "uplink";
> +				phy-mode = "2500base-x";
> +				managed = "in-band-status";
> +				sfp = <&sfp_eth1>;
> +			};
> +		};
> +	};
> +};
> -- 
> 2.41.0
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts b/arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts
index 57fc698e55d0..d6d37a1f6f38 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-eDPU.dts
@@ -12,3 +12,50 @@  / {
 &eth0 {
 	phy-mode = "2500base-x";
 };
+
+/*
+ * External MV88E6361 switch is only available on v2 of the board.
+ * U-Boot will enable the MDIO bus and switch nodes.
+ */
+&mdio {
+	status = "disabled";
+	pinctrl-names = "default";
+	pinctrl-0 = <&smi_pins>;
+
+	/* Actual device is MV88E6361 */
+	switch: switch@0 {
+		compatible = "marvell,mv88e6190";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0>;
+		status = "disabled";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				label = "cpu";
+				phy-mode = "2500base-x";
+				managed = "in-band-status";
+				ethernet = <&eth0>;
+			};
+
+			port@9 {
+				reg = <9>;
+				label = "downlink";
+				phy-mode = "2500base-x";
+				managed = "in-band-status";
+			};
+
+			port@a {
+				reg = <10>;
+				label = "uplink";
+				phy-mode = "2500base-x";
+				managed = "in-band-status";
+				sfp = <&sfp_eth1>;
+			};
+		};
+	};
+};