diff mbox series

[v2,1/4] drm/xe/gsc: add HECI2 register offsets

Message ID 20230914080138.4178295-2-alexander.usyskin@intel.com
State New
Headers
Series drm/xe/gsc: add initial gsc support |

Commit Message

Usyskin, Alexander Sept. 14, 2023, 8:01 a.m. UTC 
  From: Vitaly Lubart <vitaly.lubart@intel.com>

Add HECI2 register offsets for DG1 and DG2 to regs/xe_regs.h

Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_regs.h | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Rodrigo Vivi Sept. 18, 2023, 4:07 p.m. UTC | #1 
On Thu, Sep 14, 2023 at 11:01:35AM +0300, Alexander Usyskin wrote:
> From: Vitaly Lubart <vitaly.lubart@intel.com>
> 
> Add HECI2 register offsets for DG1 and DG2 to regs/xe_regs.h
> 
> Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_regs.h | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
> index 39d7b0740bf0..4cbc3062cb9a 100644
> --- a/drivers/gpu/drm/xe/regs/xe_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_regs.h
> @@ -33,6 +33,10 @@
>  #define XEHPC_BCS6_RING_BASE			0x3ea000
>  #define XEHPC_BCS7_RING_BASE			0x3ec000
>  #define XEHPC_BCS8_RING_BASE			0x3ee000
> +
> +#define DG1_GSC_HECI2_BASE                      0x00259000
> +#define DG2_GSC_HECI2_BASE                      0x00374000

matches the i915 ones, so

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


> +
>  #define GSCCS_RING_BASE				0x11a000
>  #define   GT_WAIT_SEMAPHORE_INTERRUPT		REG_BIT(11)
>  #define   GT_CONTEXT_SWITCH_INTERRUPT		REG_BIT(8)
> -- 
> 2.34.1
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
index 39d7b0740bf0..4cbc3062cb9a 100644
--- a/drivers/gpu/drm/xe/regs/xe_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_regs.h
@@ -33,6 +33,10 @@ 
 #define XEHPC_BCS6_RING_BASE			0x3ea000
 #define XEHPC_BCS7_RING_BASE			0x3ec000
 #define XEHPC_BCS8_RING_BASE			0x3ee000
+
+#define DG1_GSC_HECI2_BASE                      0x00259000
+#define DG2_GSC_HECI2_BASE                      0x00374000
+
 #define GSCCS_RING_BASE				0x11a000
 #define   GT_WAIT_SEMAPHORE_INTERRUPT		REG_BIT(11)
 #define   GT_CONTEXT_SWITCH_INTERRUPT		REG_BIT(8)