From patchwork Thu Sep 14 04:47:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 139997 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp749582vqi; Thu, 14 Sep 2023 19:06:37 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFWcrZcRqtnKkPf7AA1y4GfSRheqDJsYFOQE1Ccg6/BjjaG+LEuUPHtG4+yw+VeyUvBDoV/ X-Received: by 2002:a17:90b:19c5:b0:274:4f21:deae with SMTP id nm5-20020a17090b19c500b002744f21deaemr221660pjb.35.1694743596804; Thu, 14 Sep 2023 19:06:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1694743596; cv=none; d=google.com; s=arc-20160816; b=s7JkZmTQLkTV2j/VrsInk4FIwHLb5Wz5lxsqEuRauG3BUbIFnQ+7gkmBTDKjNj/ey+ VBhpGotJztLaC/xS3K7Krt0WVIlYKwO0E7AnwBwR/zgYmurnug+V9pBmF7hOpO9ZYvDB TCA1JQf8mjg8Jj+IdEz6VMqZ8/su2QntyB0z1iaNoQFEUkO5BC5c+zMBQmoLzzs5IrRd d1M5fFEvCDf2P1QZVkJ8ln0Jf7z9EQF+AR0SSduOJNOMwsw+Bn5D2IujxXO+K4CvzDIl ZAPnCnXQQceTCLcdbLArjSkzck/z6JvdRtC2ZNEq2Dhcjo5UgtTzNYuG2mGcoHp6BwOC G9PA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=zvw8/IPZQmjZB2OK/wTPQpB6D4w6hzDyR8S3ZsxCQB8=; fh=jqCbnajAXgJ+s7A1aA7DOHJD13/+EpD442pw8d+Ofss=; b=S7WkZLxBzXN6iQso+rZevpa/f9XQ5AdNSYLKbG/JV1mfZMLR0neGzMEMuft+ly4E8R 9h2DMEd21uZY8zI+SnfjRmkzEkI30Mv4QRkCYgGY3HQpBFhYXFOW2GJ1IQxIzxRwEvYY JRN1CnO8bVwjOA/aRr8D43qPDDLfgtX5fVYuewkcKbwPiwlQ/ugoCRfW6Ii7m2br4SOS mluTl0lVt5aCa0/VLRXxcVx2Gyl3XMsdI6tHA1fRsneFSA3MrdjOmQIH3c3QFQrCz9/M qEQgOiafIvGd1Ew0ZYqV+OxdO9gcD7P3xSN7ooG+skpeGuy1ve6oSoD3WxxoNyggpj8+ YEhw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=PvQx25jr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from howler.vger.email (howler.vger.email. [23.128.96.34]) by mx.google.com with ESMTPS id oo9-20020a17090b1c8900b002680f00f8f3si2760500pjb.17.2023.09.14.19.06.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Sep 2023 19:06:36 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) client-ip=23.128.96.34; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=PvQx25jr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id EEACF84EAC74; Wed, 13 Sep 2023 22:19:57 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235239AbjINFTg (ORCPT + 35 others); Thu, 14 Sep 2023 01:19:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49184 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234819AbjINFTS (ORCPT ); Thu, 14 Sep 2023 01:19:18 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D40C91BD0; Wed, 13 Sep 2023 22:19:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1694668754; x=1726204754; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CMTJxT2//f8H29ZvTGYte/VGxyI608K6t1MzstL2q6M=; b=PvQx25jrRD5MwcXXw0b9ykhG/OzEF44aWUuSHERF6XKcnrdjpwBSKjpo VDNgukIpcWqNXGO+C4OHPn0ZXEpv5kt7WJAuKIuvZdKlfcfSBNPZ9urEn 68QUKBRrrJfOER6xvkzb+ELN9vlrT8EYp9vKw4I9eW7f1MLegvWex653E Hyz+1Vk8MCItn4AAju53aE6Q+yz49NodA38k8AGSmz/19MVmI1NZtS20X eoHIljqGEPpgOh1OlXgFtS2LPgJ+8jQxHHyD+pX2ldjOBpW3rs3io/jLN 4X7xd1F/A3gVWshBOfpKt6MfwqOWtE7vTzf1BEePO9osmIwg0BZuki795 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10832"; a="382661143" X-IronPort-AV: E=Sophos;i="6.02,145,1688454000"; d="scan'208";a="382661143" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Sep 2023 22:17:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10832"; a="779488752" X-IronPort-AV: E=Sophos;i="6.02,145,1688454000"; d="scan'208";a="779488752" Received: from unknown (HELO fred..) ([172.25.112.68]) by orsmga001.jf.intel.com with ESMTP; 13 Sep 2023 22:17:31 -0700 From: Xin Li To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org, linux-hyperv@vger.kernel.org, kvm@vger.kernel.org, xen-devel@lists.xenproject.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, luto@kernel.org, pbonzini@redhat.com, seanjc@google.com, peterz@infradead.org, jgross@suse.com, ravi.v.shankar@intel.com, mhiramat@kernel.org, andrew.cooper3@citrix.com, jiangshanlai@gmail.com Subject: [PATCH v10 06/38] Documentation/x86/64: Add a documentation for FRED Date: Wed, 13 Sep 2023 21:47:33 -0700 Message-Id: <20230914044805.301390-7-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230914044805.301390-1-xin3.li@intel.com> References: <20230914044805.301390-1-xin3.li@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Wed, 13 Sep 2023 22:19:58 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777067461744637481 X-GMAIL-MSGID: 1777067461744637481 Briefly introduce FRED, and its advantages compared to IDT. Signed-off-by: Xin Li --- Documentation/arch/x86/x86_64/fred.rst | 98 +++++++++++++++++++++++++ Documentation/arch/x86/x86_64/index.rst | 1 + 2 files changed, 99 insertions(+) create mode 100644 Documentation/arch/x86/x86_64/fred.rst diff --git a/Documentation/arch/x86/x86_64/fred.rst b/Documentation/arch/x86/x86_64/fred.rst new file mode 100644 index 000000000000..a4ebb95f92c8 --- /dev/null +++ b/Documentation/arch/x86/x86_64/fred.rst @@ -0,0 +1,98 @@ +.. SPDX-License-Identifier: GPL-2.0 + +========================================= +Flexible Return and Event Delivery (FRED) +========================================= + +Overview +======== + +The FRED architecture defines simple new transitions that change +privilege level (ring transitions). The FRED architecture was +designed with the following goals: + +1) Improve overall performance and response time by replacing event + delivery through the interrupt descriptor table (IDT event + delivery) and event return by the IRET instruction with lower + latency transitions. + +2) Improve software robustness by ensuring that event delivery + establishes the full supervisor context and that event return + establishes the full user context. + +The new transitions defined by the FRED architecture are FRED event +delivery and, for returning from events, two FRED return instructions. +FRED event delivery can effect a transition from ring 3 to ring 0, but +it is used also to deliver events incident to ring 0. One FRED +instruction (ERETU) effects a return from ring 0 to ring 3, while the +other (ERETS) returns while remaining in ring 0. Collectively, FRED +event delivery and the FRED return instructions are FRED transitions. + +In addition to these transitions, the FRED architecture defines a new +instruction (LKGS) for managing the state of the GS segment register. +The LKGS instruction can be used by 64-bit operating systems that do +not use the new FRED transitions. + +Furthermore, the FRED architecture is easy to extend for future CPU +architectures. + +Software based event dispatching +================================ + +FRED operates differently from IDT in terms of event handling. Instead +of directly dispatching an event to its handler based on the event +vector, FRED requires the software to dispatch an event to its handler +based on both the event's type and vector. Therefore, an event dispatch +framework must be implemented to facilitate the event-to-handler +dispatch process. The FRED event dispatch framework takes control +once an event is delivered, and employs a two-level dispatch. + +The first level dispatching is event type based, and the second level +dispatching is event vector based. + +Full supervisor/user context +============================ + +FRED event delivery atomically save and restore full supervisor/user +context upon event delivery and return. Thus it avoids the problem of +transient states due to %cr2 and/or %dr6, and it is no longer needed +to handle all the ugly corner cases caused by half baked entry states. + +FRED allows explicit unblock of NMI with new event return instructions +ERETS/ERETU, avoiding the mess caused by IRET which unconditionally +unblocks NMI, e.g., when an exception happens during NMI handling. + +FRED always restores the full value of %rsp, thus ESPFIX is no longer +needed when FRED is enabled. + +LKGS +==== + +LKGS behaves like the MOV to GS instruction except that it loads the +base address into the IA32_KERNEL_GS_BASE MSR instead of the GS +segment’s descriptor cache. With LKGS, it ends up with avoiding +mucking with kernel GS, i.e., an operating system can always operate +with its own GS base address. + +Because FRED event delivery from ring 3 swaps the value of the GS base +address and that of the IA32_KERNEL_GS_BASE MSR, and ERETU swaps the +value of the GS base address and that of the IA32_KERNEL_GS_BASE MSR, +plus the introduction of LKGS instruction, the SWAPGS instruction is +no longer needed when FRED is enabled, thus is disallowed (#UD). + +Stack levels +============ + +4 stack levels 0~3 are introduced to replace the nonreentrant IST for +event handling, and each stack level should be configured to use a +dedicated stack. + +The current stack level could be unchanged or go higher upon FRED +event delivery. If unchanged, the CPU keeps using the current event +stack. If higher, the CPU switches to a new event stack specified by +the MSR of the new stack level, i.e., MSR_IA32_FRED_RSP{1,2,3}. + +Only execution of a FRED return instruction ERET{U,S}, could lower +the current stack level, causing the CPU to switch back to the stack +it was on before a previous event delivery that promoted the stack +level. diff --git a/Documentation/arch/x86/x86_64/index.rst b/Documentation/arch/x86/x86_64/index.rst index a56070fc8e77..ad15e9bd623f 100644 --- a/Documentation/arch/x86/x86_64/index.rst +++ b/Documentation/arch/x86/x86_64/index.rst @@ -15,3 +15,4 @@ x86_64 Support cpu-hotplug-spec machinecheck fsgs + fred