Message ID | 20230913114711.2937844-2-n-yadav@ti.com |
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State | New |
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[2620:137:e000::3:2]) by mx.google.com with ESMTPS id w8-20020a63f508000000b0054ff53233f2si10380283pgh.567.2023.09.13.09.10.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Sep 2023 09:10:10 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) client-ip=2620:137:e000::3:2; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=qBTRVlcV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by agentk.vger.email (Postfix) with ESMTP id 4CBE28099CC1; Wed, 13 Sep 2023 04:48:04 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at agentk.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240441AbjIMLri (ORCPT <rfc822;pwkd43@gmail.com> + 36 others); Wed, 13 Sep 2023 07:47:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45554 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237163AbjIMLra (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Wed, 13 Sep 2023 07:47:30 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AA2EB19AF; Wed, 13 Sep 2023 04:47:26 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 38DBlF6i034988; Wed, 13 Sep 2023 06:47:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1694605635; bh=qLnPxdmrn3BTI0+nFi+wG309MiqnPoLWlUA/axflbOQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=qBTRVlcVLA4ZP/MWfqxW6oAhtFugHPd5R/v6GBNRBIfOuYuwawValHiByC0sEKzkm cl89QfxKDYZzfbWleJtst5j9caldwGP4ZmhOKE+EfALP0x3U3FH+PCOC/2yMrIb83N Oxf3olAZaA0qqScK8g6QR60BZ1HfZjkm2wMeMMhY= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 38DBlFv0113438 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 13 Sep 2023 06:47:15 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 13 Sep 2023 06:47:14 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 13 Sep 2023 06:47:14 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 38DBlDqj001933; Wed, 13 Sep 2023 06:47:14 -0500 From: Nitin Yadav <n-yadav@ti.com> To: <nm@ti.com>, <vigneshr@ti.com>, <rogerq@ti.com> CC: <kristo@kernel.org>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>, <catalin.marinas@arm.com>, <will@kernel.org>, <linux-arm-kernel@lists.infradead.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH 1/3] arm64: dts: ti: Add GPMC NAND support Date: Wed, 13 Sep 2023 17:17:09 +0530 Message-ID: <20230913114711.2937844-2-n-yadav@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230913114711.2937844-1-n-yadav@ti.com> References: <20230913114711.2937844-1-n-yadav@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Wed, 13 Sep 2023 04:48:04 -0700 (PDT) X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1776939340345354910 X-GMAIL-MSGID: 1776939340345354910 |
Series |
Add support for GPMC NAND
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Commit Message
Nitin Yadav
Sept. 13, 2023, 11:47 a.m. UTC
Add support for AM62Q NAND card: X8 NAND EXPANSION
BOARD card (PROC143E1) for AM62x LP SK board.
Signed-off-by: Nitin Yadav <n-yadav@ti.com>
---
arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 29 ++++++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-am62.dtsi | 2 ++
2 files changed, 31 insertions(+)
Comments
On 13/09/2023 13:47, Nitin Yadav wrote: > Add support for AM62Q NAND card: X8 NAND EXPANSION > BOARD card (PROC143E1) for AM62x LP SK board. > > Signed-off-by: Nitin Yadav <n-yadav@ti.com> > --- > arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 29 ++++++++++++++++++++++++ > arch/arm64/boot/dts/ti/k3-am62.dtsi | 2 ++ > 2 files changed, 31 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi > index 284b90c94da8..e93e79d8083f 100644 > --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi > @@ -955,4 +955,33 @@ mcasp2: audio-controller@2b20000 { > power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; > status = "disabled"; > }; > + gpmc0: memory-controller@3b000000 { > + status = "disabled"; status is never first in DTSI. Really, where did you see such code? > + compatible = "ti,am64-gpmc"; > + power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; First is compatible, second is reg/reg-names/ranges. Best regards, Krzysztof
Hi Krzysztof, On 14/09/23 11:57, Krzysztof Kozlowski wrote: > On 13/09/2023 13:47, Nitin Yadav wrote: >> Add support for AM62Q NAND card: X8 NAND EXPANSION >> BOARD card (PROC143E1) for AM62x LP SK board. >> >> Signed-off-by: Nitin Yadav <n-yadav@ti.com> >> --- >> arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 29 ++++++++++++++++++++++++ >> arch/arm64/boot/dts/ti/k3-am62.dtsi | 2 ++ >> 2 files changed, 31 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi >> index 284b90c94da8..e93e79d8083f 100644 >> --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi >> +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi >> @@ -955,4 +955,33 @@ mcasp2: audio-controller@2b20000 { >> power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; >> status = "disabled"; >> }; >> + gpmc0: memory-controller@3b000000 { >> + status = "disabled"; > > status is never first in DTSI. Really, where did you see such code? Thank for pointing out, Will send a revised version. > >> + compatible = "ti,am64-gpmc"; >> + power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; > > First is compatible, second is reg/reg-names/ranges. > > > Best regards, > Krzysztof >
On 14:56-20230914, Nitin Yadav wrote: > Hi Krzysztof, > > On 14/09/23 11:57, Krzysztof Kozlowski wrote: > > On 13/09/2023 13:47, Nitin Yadav wrote: > >> Add support for AM62Q NAND card: X8 NAND EXPANSION > >> BOARD card (PROC143E1) for AM62x LP SK board. Commit message is all too wrong as well. Sigh. > >> > >> Signed-off-by: Nitin Yadav <n-yadav@ti.com> > >> --- > >> arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 29 ++++++++++++++++++++++++ > >> arch/arm64/boot/dts/ti/k3-am62.dtsi | 2 ++ > >> 2 files changed, 31 insertions(+) > >> > >> diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi > >> index 284b90c94da8..e93e79d8083f 100644 > >> --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi > >> +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi > >> @@ -955,4 +955,33 @@ mcasp2: audio-controller@2b20000 { > >> power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; > >> status = "disabled"; > >> }; > >> + gpmc0: memory-controller@3b000000 { > >> + status = "disabled"; > > > > status is never first in DTSI. Really, where did you see such code? > Thank for pointing out, Will send a revised version. GPMC is not functional without board specific interface configuration such as pinmux. this approach, in fact is all over the place now and discussed in the mailing list multiple times now. What is missing here is the documentation of the constraints as to why it is set as disabled by default. > > > >> + compatible = "ti,am64-gpmc"; > >> + power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; > > > > First is compatible, second is reg/reg-names/ranges. > > > > > > Best regards, > > Krzysztof > > > > -- > Regards, > Nitin
On 14/09/23 21:34, Nishanth Menon wrote: > On 14:56-20230914, Nitin Yadav wrote: >> Hi Krzysztof, >> >> On 14/09/23 11:57, Krzysztof Kozlowski wrote: >>> On 13/09/2023 13:47, Nitin Yadav wrote: >>>> Add support for AM62Q NAND card: X8 NAND EXPANSION >>>> BOARD card (PROC143E1) for AM62x LP SK board. > > Commit message is all too wrong as well. Sigh. > >>>> >>>> Signed-off-by: Nitin Yadav <n-yadav@ti.com> >>>> --- >>>> arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 29 ++++++++++++++++++++++++ >>>> arch/arm64/boot/dts/ti/k3-am62.dtsi | 2 ++ >>>> 2 files changed, 31 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi >>>> index 284b90c94da8..e93e79d8083f 100644 >>>> --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi >>>> +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi >>>> @@ -955,4 +955,33 @@ mcasp2: audio-controller@2b20000 { >>>> power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; >>>> status = "disabled"; >>>> }; >>>> + gpmc0: memory-controller@3b000000 { >>>> + status = "disabled"; >>> >>> status is never first in DTSI. Really, where did you see such code? >> Thank for pointing out, Will send a revised version. > > GPMC is not functional without board specific interface configuration > such as pinmux. this approach, in fact is all over the place now and > discussed in the mailing list multiple times now. > > What is missing here is the documentation of the constraints as to why > it is set as disabled by default. gpmc nand is only am62x lp sk in am62x series. it has pinmux conflict with macsp1, so disabling gpmc & elm by default for other am62 series. For am62x lpsk in overlay macsp1 is disabled. > > >>> >>>> + compatible = "ti,am64-gpmc"; >>>> + power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; >>> >>> First is compatible, second is reg/reg-names/ranges. >>> >>> >>> Best regards, >>> Krzysztof >>> >> >> -- >> Regards, >> Nitin >
Hi Nitin, On 13.9.2023 14.47, Nitin Yadav wrote: > Add support for AM62Q NAND card: X8 NAND EXPANSION > BOARD card (PROC143E1) for AM62x LP SK board. This patch is not adding NAND support but GPMC and ELM nodes. > > Signed-off-by: Nitin Yadav <n-yadav@ti.com> > --- > arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 29 ++++++++++++++++++++++++ > arch/arm64/boot/dts/ti/k3-am62.dtsi | 2 ++ > 2 files changed, 31 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi > index 284b90c94da8..e93e79d8083f 100644 > --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi > @@ -955,4 +955,33 @@ mcasp2: audio-controller@2b20000 { > power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; > status = "disabled"; > }; > + gpmc0: memory-controller@3b000000 { > + status = "disabled"; > + compatible = "ti,am64-gpmc"; > + power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; > + clocks = <&k3_clks 80 0>; > + clock-names = "fck"; > + reg = <0x00 0x03b000000 0x00 0x400>, > + <0x00 0x050000000 0x00 0x8000000>; > + reg-names = "cfg", "data"; > + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; > + gpmc,num-cs = <3>; > + gpmc,num-waitpins = <2>; > + #address-cells = <2>; > + #size-cells = <1>; > + interrupt-controller; > + #interrupt-cells = <2>; > + gpio-controller; > + #gpio-cells = <2>; > + }; > + > + elm0: ecc@25010000 { > + status = "disabled"; > + compatible = "ti,am3352-elm"; > + reg = <0x00 0x25010000 0x00 0x2000>; > + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; > + power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; > + clocks = <&k3_clks 54 0>; > + clock-names = "fck"; > + }; > }; > diff --git a/arch/arm64/boot/dts/ti/k3-am62.dtsi b/arch/arm64/boot/dts/ti/k3-am62.dtsi > index 11f14eef2d44..f7d8aad0a016 100644 > --- a/arch/arm64/boot/dts/ti/k3-am62.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-am62.dtsi > @@ -76,6 +76,8 @@ cbass_main: bus@f0000 { > <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */ > <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ > <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ > + <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */ > + <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */ > > /* MCU Domain Range */ > <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
On 14:53-20230915, Nitin Yadav wrote: > > > On 14/09/23 21:34, Nishanth Menon wrote: > > On 14:56-20230914, Nitin Yadav wrote: > >> Hi Krzysztof, > >> > >> On 14/09/23 11:57, Krzysztof Kozlowski wrote: > >>> On 13/09/2023 13:47, Nitin Yadav wrote: > >>>> Add support for AM62Q NAND card: X8 NAND EXPANSION > >>>> BOARD card (PROC143E1) for AM62x LP SK board. > > > > Commit message is all too wrong as well. Sigh. > > > >>>> > >>>> Signed-off-by: Nitin Yadav <n-yadav@ti.com> > >>>> --- > >>>> arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 29 ++++++++++++++++++++++++ > >>>> arch/arm64/boot/dts/ti/k3-am62.dtsi | 2 ++ > >>>> 2 files changed, 31 insertions(+) > >>>> > >>>> diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi > >>>> index 284b90c94da8..e93e79d8083f 100644 > >>>> --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi > >>>> +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi > >>>> @@ -955,4 +955,33 @@ mcasp2: audio-controller@2b20000 { > >>>> power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; > >>>> status = "disabled"; > >>>> }; > >>>> + gpmc0: memory-controller@3b000000 { > >>>> + status = "disabled"; > >>> > >>> status is never first in DTSI. Really, where did you see such code? > >> Thank for pointing out, Will send a revised version. > > > > GPMC is not functional without board specific interface configuration > > such as pinmux. this approach, in fact is all over the place now and > > discussed in the mailing list multiple times now. > > > > What is missing here is the documentation of the constraints as to why > > it is set as disabled by default. > gpmc nand is only am62x lp sk in am62x series. it has pinmux conflict > with macsp1, so disabling gpmc & elm by default for other am62 series. > For am62x lpsk in overlay macsp1 is disabled. When introducing a patch for SoC dtsi - explain in commit message and code comments from the SoC's perspective, not the specific board perspective.
diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index 284b90c94da8..e93e79d8083f 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -955,4 +955,33 @@ mcasp2: audio-controller@2b20000 { power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; status = "disabled"; }; + gpmc0: memory-controller@3b000000 { + status = "disabled"; + compatible = "ti,am64-gpmc"; + power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 80 0>; + clock-names = "fck"; + reg = <0x00 0x03b000000 0x00 0x400>, + <0x00 0x050000000 0x00 0x8000000>; + reg-names = "cfg", "data"; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + gpmc,num-cs = <3>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + elm0: ecc@25010000 { + status = "disabled"; + compatible = "ti,am3352-elm"; + reg = <0x00 0x25010000 0x00 0x2000>; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 54 0>; + clock-names = "fck"; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62.dtsi b/arch/arm64/boot/dts/ti/k3-am62.dtsi index 11f14eef2d44..f7d8aad0a016 100644 --- a/arch/arm64/boot/dts/ti/k3-am62.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62.dtsi @@ -76,6 +76,8 @@ cbass_main: bus@f0000 { <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */ <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ + <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */ + <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */ /* MCU Domain Range */ <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,