From patchwork Tue Sep 12 07:58:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 138246 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9ecd:0:b0:3f2:4152:657d with SMTP id t13csp483587vqx; Tue, 12 Sep 2023 08:23:15 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE2HF/w0ggkU2BwZS3v+2T3g4k5U2gUrh3v3KQA830elLD/F2fB5uCxIFEBUJzaOAm54CkW X-Received: by 2002:a05:6a00:84a:b0:68c:a81:4368 with SMTP id q10-20020a056a00084a00b0068c0a814368mr125503pfk.6.1694532195472; Tue, 12 Sep 2023 08:23:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1694532195; cv=none; d=google.com; s=arc-20160816; b=AZPY4LlN7pPoharSnD+BFRuOf3NO9dAul/NjmFTFMwnJ5hjVglWwi+Wh8q1VGM0q0C 2Pqm4/Y44bG6t8Lv/8qW9UqZyQctWFigzKClNFNy57on/S4bzA6XxRsRMhDBYS+vOOAZ e4z57kNjtKnxiE/TIitHrg9ifM5bp30ING3yvfbfvouDVI8pFmx90YcB+NaMbpaKwo6g ur8BMBtCgjzuTcuNzpwZphEK7AC6dyZEhs++icyp3AU9bIHuEDGDNRi+U02gLpFRF1Ih 1QfNAcbn7fgSMnLWCXPY7Rr+Q6S8CZFOXkrPdvL/E9T3eKDRlc9oHsgcx+DEpdIYWGyl bATA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=Q4ru7NAfdX5E2q0WOPskDN2at23E5jYbJEoHUeyYgF4=; fh=u57tXYamzTrJA+Ht8n1u7SfTMptrQaIb6LVW+jsaYf4=; b=IdVpr4uiRWAmJyQKFPxGpIoSZdUV5ZMtkSxrhJCFvOhd+i6ViXBBho0o7gxWqMsEhr quaYpbBoUmPNDgf1VwDfWTMXNpfHgFdgU2irmNnS1z/P83fDT0lYfhxAmEtvalWxGoRy YvSj+Q0y5q+QmjfTuaryPah44JHxs3yCbW0oPYNFs8QtVMSbRAClxYYDXKQBaxsJJhBp s2jOTKHAbpnBtdw0c8AL/JN7QeeVzyK1qKcDnrcnz3PqmtP0ymBOKpH5Lq+0JlFyx691 0Sh+7tIozLArGFTABNQZbh7BM3sfiHF+i99MxtxUiGLaARqj07f14jEXUihWra3QYurJ KCCQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=TcYrBqZ+; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from pete.vger.email (pete.vger.email. [2620:137:e000::3:6]) by mx.google.com with ESMTPS id bv185-20020a632ec2000000b0056357813fc2si7828350pgb.183.2023.09.12.08.23.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Sep 2023 08:23:15 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) client-ip=2620:137:e000::3:6; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=TcYrBqZ+; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id 57670819D9E6; Tue, 12 Sep 2023 01:03:34 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232118AbjILIAP (ORCPT + 39 others); Tue, 12 Sep 2023 04:00:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54148 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232101AbjILH6s (ORCPT ); Tue, 12 Sep 2023 03:58:48 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 86CB82122 for ; Tue, 12 Sep 2023 00:58:14 -0700 (PDT) Message-ID: <20230912065501.899886649@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1694505492; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Q4ru7NAfdX5E2q0WOPskDN2at23E5jYbJEoHUeyYgF4=; b=TcYrBqZ+SVaKkchzBHbrsg1CWP5Totia+mjt1S62DOrsjqpzr2myhzDmfFIJgcXS687mbW pFOMyhPYw8jpSde+jptSKfoqopy4OwRcIptOPXRzK3Oy5VLwwXhWEtJ9fCI3AlPCRon+cv 0SUb4ErB0vBRTyqpalOAIPEe06ER+OkXDhub2TxCTRAuymf8r+Az97vp6QrJMq1+shcrMV GxRR72VZQWjF3Otu8SJb/S6twc+kG986u3b6ZMexDk7rlVcd0+Po/ZpZhTrZDBkCIIMEOc BNBe5aeMhlLyefImUH00Ui4UDUfgY3rvbqsL5x0SMOu5F40pjGAxRhODtXCbxQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1694505492; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Q4ru7NAfdX5E2q0WOPskDN2at23E5jYbJEoHUeyYgF4=; b=UWxqK4b75j2w6T5PE8NCAeDHJEJhASRyEfzwys0UndjdljmpMh3VCP9JYa9PpsFxOGYaUG eUkfOtYtJnKPFCDA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , "Chang S. Bae" , Arjan van de Ven , Nikolay Borisov Subject: [patch V3 18/30] x86/microcode: Handle "nosmt" correctly References: <20230912065249.695681286@linutronix.de> MIME-Version: 1.0 Date: Tue, 12 Sep 2023 09:58:12 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Tue, 12 Sep 2023 01:03:34 -0700 (PDT) X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1776845791582482014 X-GMAIL-MSGID: 1776845791582482014 From: Thomas Gleixner On CPUs where microcode loading is not NMI safe the SMT sibling which is parked in one of the play_dead() variants, these parked CPUs still react on NMIs. So if a NMI hits while the primary thread updates the microcode the resulting behaviour is undefined. The default play_dead() implementation on modern CPUs is using MWAIT, which is not guaranteed to be safe against an microcode update which affects MWAIT. Take the cpus_booted_once_mask into account to detect this case and refuse to load late if the vendor specific driver does not advertise that late loading is NMI safe. AMD stated that this is safe, so mark the AMD driver accordingly. This requirement will be partially lifted in later changes. Signed-off-by: Thomas Gleixner --- arch/x86/Kconfig | 2 - arch/x86/kernel/cpu/microcode/amd.c | 9 +++-- arch/x86/kernel/cpu/microcode/core.c | 51 +++++++++++++++++++------------ arch/x86/kernel/cpu/microcode/internal.h | 13 +++---- 4 files changed, 44 insertions(+), 31 deletions(-) --- --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1314,7 +1314,7 @@ config MICROCODE config MICROCODE_LATE_LOADING bool "Late microcode loading (DANGEROUS)" default n - depends on MICROCODE + depends on MICROCODE && SMP help Loading microcode late, when the system is up and executing instructions is a tricky business and should be avoided if possible. Just the sequence --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -948,10 +948,11 @@ static void microcode_fini_cpu_amd(int c } static struct microcode_ops microcode_amd_ops = { - .request_microcode_fw = request_microcode_amd, - .collect_cpu_info = collect_cpu_info_amd, - .apply_microcode = apply_microcode_amd, - .microcode_fini_cpu = microcode_fini_cpu_amd, + .request_microcode_fw = request_microcode_amd, + .collect_cpu_info = collect_cpu_info_amd, + .apply_microcode = apply_microcode_amd, + .microcode_fini_cpu = microcode_fini_cpu_amd, + .nmi_safe = true, }; struct microcode_ops * __init init_amd_microcode(void) --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -326,23 +326,6 @@ static struct platform_device *microcode */ #define SPINUNIT 100 /* 100 nsec */ -static int check_online_cpus(void) -{ - unsigned int cpu; - - /* - * Make sure all CPUs are online. It's fine for SMT to be disabled if - * all the primary threads are still online. - */ - for_each_present_cpu(cpu) { - if (topology_is_primary_thread(cpu) && !cpu_online(cpu)) { - pr_err("Not all CPUs online, aborting microcode update.\n"); - return -EINVAL; - } - } - - return 0; -} static atomic_t late_cpus_in; static atomic_t late_cpus_out; @@ -459,6 +442,35 @@ static int microcode_reload_late(void) return ret; } +/* + * Ensure that all required CPUs which are present and have been booted + * once are online. + * + * To pass this check, all primary threads must be online. + * + * If the microcode load is not safe against NMI then all SMT threads + * must be online as well because they still react on NMI when they are + * soft-offlined and parked in one of the play_dead() variants. So if a + * NMI hits while the primary thread updates the microcode the resulting + * behaviour is undefined. The default play_dead() implementation on + * modern CPUs is using MWAIT, which is also not guaranteed to be safe + * against a microcode update which affects MWAIT. + */ +static bool ensure_cpus_are_online(void) +{ + unsigned int cpu; + + for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) { + if (!cpu_online(cpu)) { + if (topology_is_primary_thread(cpu) || !microcode_ops->nmi_safe) { + pr_err("CPU %u not online\n", cpu); + return false; + } + } + } + return true; +} + static ssize_t reload_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t size) @@ -474,9 +486,10 @@ static ssize_t reload_store(struct devic cpus_read_lock(); - ret = check_online_cpus(); - if (ret) + if (!ensure_cpus_are_online()) { + ret = -EBUSY; goto put; + } tmp_ret = microcode_ops->request_microcode_fw(bsp, µcode_pdev->dev); if (tmp_ret != UCODE_NEW) --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -20,18 +20,17 @@ enum ucode_state { struct microcode_ops { enum ucode_state (*request_microcode_fw)(int cpu, struct device *dev); - void (*microcode_fini_cpu)(int cpu); /* - * The generic 'microcode_core' part guarantees that - * the callbacks below run on a target cpu when they - * are being called. + * The generic 'microcode_core' part guarantees that the callbacks + * below run on a target cpu when they are being called. * See also the "Synchronization" section in microcode_core.c. */ - enum ucode_state (*apply_microcode)(int cpu); - int (*collect_cpu_info)(int cpu, struct cpu_signature *csig); - void (*finalize_late_load)(int result); + enum ucode_state (*apply_microcode)(int cpu); + int (*collect_cpu_info)(int cpu, struct cpu_signature *csig); + void (*finalize_late_load)(int result); + unsigned int nmi_safe : 1; }; extern struct ucode_cpu_info ucode_cpu_info[];