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[23.128.96.38]) by mx.google.com with ESMTPS id k7-20020a633d07000000b00565e98183d6si9097041pga.626.2023.09.12.17.49.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Sep 2023 17:49:44 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) client-ip=23.128.96.38; Authentication-Results: mx.google.com; dkim=pass header.i=@kernkonzept.com header.s=mx1 header.b=VW2OT9ME; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernkonzept.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id E598580F7293; Tue, 12 Sep 2023 07:31:37 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235995AbjILObG (ORCPT + 37 others); Tue, 12 Sep 2023 10:31:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34208 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235968AbjILOa7 (ORCPT ); Tue, 12 Sep 2023 10:30:59 -0400 Received: from mx.kernkonzept.com (serv1.kernkonzept.com [IPv6:2a01:4f8:1c1c:b490::2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EC88FCC7; Tue, 12 Sep 2023 07:30:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=kernkonzept.com; s=mx1; h=Cc:To:In-Reply-To:References:Message-Id: Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date:From: Reply-To:Content-ID:Content-Description; bh=d8aTXSfXKUiK1Xyz5/399gXFzKYpAJm1Z7s+7n6AgiA=; b=VW2OT9MEsssDRMkwh3Uc/UV/sU ZvJI7PAAq82QQLTuNMbZ4JB2NvSLaDDhCPziIIIXjoZuw5Si5G7cBoMsE6xSHv21w48NpUQnK+0aS xlAPsANfObrC1zT09ttft7W+z3JCpckVRiUodnA48hUGcsuU5GRfWlotgo1sSQ/yewjwa4Ld/fYdl nImSY9IBb27xYyDp8bkpdUjxhq30ecnHdGpf0m7nyf5FLHMUCl0mrXQXGHsMEw7GBj54hLCAAKRa7 hNAcKfTXX6fvIWrmTWQ9wqC2+4JOJBdElsYVcng7iofUJJ6jJIG88oT9CmsDCrBpjht7ereCuItgF jxnItlew==; Received: from [10.22.3.24] (helo=serv1.dd1.int.kernkonzept.com) by mx.kernkonzept.com with esmtpsa (TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim 4.96) id 1qg4Pk-0034i9-1z; Tue, 12 Sep 2023 16:30:52 +0200 From: Stephan Gerhold Date: Tue, 12 Sep 2023 16:30:39 +0200 Subject: [PATCH 4/4] spi: qup: Vote for interconnect bandwidth to DRAM MIME-Version: 1.0 Message-Id: <20230912-spi-qup-dvfs-v1-4-3e38aa09c2bd@kernkonzept.com> References: <20230912-spi-qup-dvfs-v1-0-3e38aa09c2bd@kernkonzept.com> In-Reply-To: <20230912-spi-qup-dvfs-v1-0-3e38aa09c2bd@kernkonzept.com> To: Mark Brown Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Stephan Gerhold X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Tue, 12 Sep 2023 07:31:38 -0700 (PDT) X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1776881431880327383 X-GMAIL-MSGID: 1776881431880327383 When the SPI QUP controller is used together with a DMA engine it needs to vote for the interconnect path to the DRAM. Otherwise it may be unable to access the memory quickly enough. The requested peak bandwidth is dependent on the SPI core/bus clock so that the bandwidth scales together with the selected SPI speed. To avoid sending votes too often the bandwidth is always requested when a transfer starts, but dropped only on runtime suspend. Runtime suspend should only happen if no transfer is active. After resumption we can defer the next vote until the first transfer actually happens. Signed-off-by: Stephan Gerhold --- The bandwidth calculation is taken over from Qualcomm's downstream/vendor driver [1]. Due to lack of documentation about the interconnect setup/behavior I cannot say exactly if this is right. Unfortunately, this is not implemented very consistently downstream... [1]: https://git.codelinaro.org/clo/la/kernel/msm-3.18/-/commit/deca0f346089d32941d6d8194ae9605554486413 --- drivers/spi/spi-qup.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c index bf043be3a2a9..e9c186bc530c 100644 --- a/drivers/spi/spi-qup.c +++ b/drivers/spi/spi-qup.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -122,11 +123,14 @@ #define SPI_DELAY_THRESHOLD 1 #define SPI_DELAY_RETRY 10 +#define SPI_BUS_WIDTH 8 + struct spi_qup { void __iomem *base; struct device *dev; struct clk *cclk; /* core clock */ struct clk *iclk; /* interface clock */ + struct icc_path *icc_path; /* interconnect to RAM */ int irq; spinlock_t lock; @@ -149,6 +153,8 @@ struct spi_qup { int mode; struct dma_slave_config rx_conf; struct dma_slave_config tx_conf; + + u32 bw_speed_hz; }; static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer); @@ -181,6 +187,23 @@ static inline bool spi_qup_is_valid_state(struct spi_qup *controller) return opstate & QUP_STATE_VALID; } +static int spi_qup_vote_bw(struct spi_qup *controller, u32 speed_hz) +{ + u32 needed_peak_bw; + int ret; + + if (controller->bw_speed_hz == speed_hz) + return 0; + + needed_peak_bw = Bps_to_icc(speed_hz * SPI_BUS_WIDTH); + ret = icc_set_bw(controller->icc_path, 0, needed_peak_bw); + if (ret) + return ret; + + controller->bw_speed_hz = speed_hz; + return 0; +} + static int spi_qup_set_state(struct spi_qup *controller, u32 state) { unsigned long loop; @@ -675,6 +698,12 @@ static int spi_qup_io_prep(struct spi_device *spi, struct spi_transfer *xfer) return -EIO; } + ret = spi_qup_vote_bw(controller, xfer->speed_hz); + if (ret) { + dev_err(controller->dev, "fail to vote for ICC bandwidth: %d\n", ret); + return -EIO; + } + controller->w_size = DIV_ROUND_UP(xfer->bits_per_word, 8); controller->n_words = xfer->len / controller->w_size; @@ -994,6 +1023,7 @@ static void spi_qup_set_cs(struct spi_device *spi, bool val) static int spi_qup_probe(struct platform_device *pdev) { struct spi_controller *host; + struct icc_path *icc_path; struct clk *iclk, *cclk; struct spi_qup *controller; struct resource *res; @@ -1019,6 +1049,11 @@ static int spi_qup_probe(struct platform_device *pdev) if (IS_ERR(iclk)) return PTR_ERR(iclk); + icc_path = devm_of_icc_get(dev, NULL); + if (IS_ERR(icc_path)) + return dev_err_probe(dev, PTR_ERR(icc_path), + "failed to get interconnect path\n"); + /* This is optional parameter */ if (of_property_read_u32(dev->of_node, "spi-max-frequency", &max_freq)) max_freq = SPI_MAX_RATE; @@ -1070,6 +1105,7 @@ static int spi_qup_probe(struct platform_device *pdev) controller->base = base; controller->iclk = iclk; controller->cclk = cclk; + controller->icc_path = icc_path; controller->irq = irq; ret = spi_qup_init_dma(host, res->start); @@ -1190,6 +1226,7 @@ static int spi_qup_pm_suspend_runtime(struct device *device) writel_relaxed(config, controller->base + QUP_CONFIG); clk_disable_unprepare(controller->cclk); + spi_qup_vote_bw(controller, 0); clk_disable_unprepare(controller->iclk); return 0; @@ -1241,6 +1278,7 @@ static int spi_qup_suspend(struct device *device) return ret; clk_disable_unprepare(controller->cclk); + spi_qup_vote_bw(controller, 0); clk_disable_unprepare(controller->iclk); return 0; }