From patchwork Mon Aug 21 04:52:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anshuman Khandual X-Patchwork-Id: 136398 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b82d:0:b0:3f2:4152:657d with SMTP id z13csp3031438vqi; Mon, 21 Aug 2023 07:11:02 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGkLT82W5ZS1f1pde+mW0DXFvrOQrp5NnS1gY24wLb5hq/gMRV3mAXuSzAkE+HwNwD2pxg8 X-Received: by 2002:a17:906:7396:b0:99e:1581:6437 with SMTP id f22-20020a170906739600b0099e15816437mr5333901ejl.46.1692627062551; Mon, 21 Aug 2023 07:11:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692627062; cv=none; d=google.com; s=arc-20160816; b=uVLXgvtMlCEg2KQVzG9BbWjl1N2yd3EI9FZQCwasWvuO4rhW5o1iv2kXqoWIVRozsR IBXsSQQxaRCz8C6oHS1xyUxYl1H7I+ngnj5ZoAr5U9A6dY+IIh0swltq54eIKW0IW+Sh spPdIbqK/JuclNEnYlo5Bo88mDoyZRi2JX8J1+PTfwe5a/FHNZu1YmQFKkWHZYQwR1zF Lz5X4B2rMXt1R/eaEm46nD6g4pCi5xhl7rFp6Xn6MZtkPZi4V/RUcAV0a2T2mZMurrqn WDKhXiFiim5uH16nqM4Vo9hU6GpgAgBWSlmRrvHOMZ/A8tCLPA0892XteY/UigADpXyU 078Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=fwxbkQZZVcevhuD1KJDwPGuwK0V4NuCuslTjKvB97B4=; fh=i7k4OkcaLUFocIK64fg5M0UL6Z7MqFc0/WYsE6IUDvI=; b=p3QbUCXzlOURqIXMWAVZyQbmc0wrHi0ZE629f85h8uwrgVv/lMN6SqeriKQ+PmGJYh R8XMxV0LFduqPTSijvsDYcjImmpHhjDyqMyJoVxXjv2lvXPCEiCyokkcfae4CbtkG2xo +cOuk9UUSGjWKrG4IEceafP1tw4kVZ9GaXb3dmz50+N2LjmaWxdMTlvVDnCwemmnGwj0 8r/tZtKHec1xhUMQ7R/Vo8PrVd8iYqBCK6cfZD0/DOXAYXB0/n2c011+11aGs51NHEsA SiewyNYyABbPks4ZxgLZFWlctfueiMDyFxPTz3AtrooRWJHBX35QK+QILAtY6hhzsGpg QcZA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id cb13-20020a170906a44d00b0099cb0ea654esi6011329ejb.1033.2023.08.21.07.10.37; Mon, 21 Aug 2023 07:11:02 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233073AbjHUEwm (ORCPT + 99 others); Mon, 21 Aug 2023 00:52:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53088 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229535AbjHUEwl (ORCPT ); Mon, 21 Aug 2023 00:52:41 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id BCA44A8; Sun, 20 Aug 2023 21:52:39 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2E56D1FB; Sun, 20 Aug 2023 21:53:20 -0700 (PDT) Received: from a077893.blr.arm.com (a077893.blr.arm.com [10.162.42.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 4ED3B3F740; Sun, 20 Aug 2023 21:52:35 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, suzuki.poulose@arm.com Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Mike Leach , James Clark , Leo Yan , Jonathan Corbet , linux-doc@vger.kernel.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Subject: [PATCH V5 2/3] coresight: etm: Make cycle count threshold user configurable Date: Mon, 21 Aug 2023 10:22:15 +0530 Message-Id: <20230821045216.641499-3-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230821045216.641499-1-anshuman.khandual@arm.com> References: <20230821045216.641499-1-anshuman.khandual@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774815598531982040 X-GMAIL-MSGID: 1774848114790796843 Cycle counting is enabled, when requested and supported but with a default threshold value ETM_CYC_THRESHOLD_DEFAULT i.e 0x100 getting into TRCCCCTLR, representing the minimum interval between cycle count trace packets. This makes cycle threshold user configurable, from the user space via perf event attributes. Although it falls back using ETM_CYC_THRESHOLD_DEFAULT, in case no explicit request. As expected it creates a sysfs file as well. /sys/bus/event_source/devices/cs_etm/format/cc_threshold New 'cc_threshold' uses 'event->attr.config3' as no more space is available in 'event->attr.config1' or 'event->attr.config2'. Cc: Suzuki K Poulose Cc: Mike Leach Cc: James Clark Cc: Leo Yan Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Mike Leach Signed-off-by: Anshuman Khandual --- drivers/hwtracing/coresight/coresight-etm-perf.c | 2 ++ drivers/hwtracing/coresight/coresight-etm4x-core.c | 9 +++++++-- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 5ca6278baff4..09f75dffae60 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -68,6 +68,7 @@ PMU_FORMAT_ATTR(preset, "config:0-3"); PMU_FORMAT_ATTR(sinkid, "config2:0-31"); /* config ID - set if a system configuration is selected */ PMU_FORMAT_ATTR(configid, "config2:32-63"); +PMU_FORMAT_ATTR(cc_threshold, "config3:0-11"); /* @@ -101,6 +102,7 @@ static struct attribute *etm_config_formats_attr[] = { &format_attr_preset.attr, &format_attr_configid.attr, &format_attr_branch_broadcast.attr, + &format_attr_cc_threshold.attr, NULL, }; diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 1308d89f58d1..9edba406f523 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -635,7 +635,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev, struct etmv4_config *config = &drvdata->config; struct perf_event_attr *attr = &event->attr; unsigned long cfg_hash; - int preset; + int preset, cc_threshold; /* Clear configuration from previous run */ memset(config, 0, sizeof(struct etmv4_config)); @@ -658,7 +658,12 @@ static int etm4_parse_event_config(struct coresight_device *csdev, if (attr->config & BIT(ETM_OPT_CYCACC)) { config->cfg |= TRCCONFIGR_CCI; /* TRM: Must program this for cycacc to work */ - config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT; + cc_threshold = attr->config3 & ETM_CYC_THRESHOLD_MASK; + if (!cc_threshold) + cc_threshold = ETM_CYC_THRESHOLD_DEFAULT; + if (cc_threshold < drvdata->ccitmin) + cc_threshold = drvdata->ccitmin; + config->ccctlr = cc_threshold; } if (attr->config & BIT(ETM_OPT_TS)) { /*