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[23.128.96.37]) by mx.google.com with ESMTPS id s30-20020a056a00179e00b00690bd5a0bc9si1755210pfg.360.2023.10.06.08.07.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Oct 2023 08:07:25 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 28DF98313345; Fri, 6 Oct 2023 08:07:16 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232711AbjJFPHL (ORCPT + 18 others); Fri, 6 Oct 2023 11:07:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57084 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232611AbjJFPHK (ORCPT ); Fri, 6 Oct 2023 11:07:10 -0400 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [IPv6:2a0a:edc0:2:b01:1d::104]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 62F14D6 for ; Fri, 6 Oct 2023 08:07:08 -0700 (PDT) Received: from dude05.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::54]) by metis.whiteo.stw.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1qomPy-00051v-5B; Fri, 06 Oct 2023 17:07:06 +0200 From: Michael Tretter Date: Fri, 06 Oct 2023 17:07:04 +0200 Subject: [PATCH v2 2/5] drm/bridge: samsung-dsim: reread ref clock before configuring PLL MIME-Version: 1.0 Message-Id: <20230818-samsung-dsim-v2-2-846603df0e0a@pengutronix.de> References: <20230818-samsung-dsim-v2-0-846603df0e0a@pengutronix.de> In-Reply-To: <20230818-samsung-dsim-v2-0-846603df0e0a@pengutronix.de> To: Inki Dae , Jagan Teki , Marek Szyprowski , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Daniel Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, kernel@pengutronix.de, Michael Tretter , Frieder Schrempf , Marco Felsch X-Mailer: b4 0.12.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::54 X-SA-Exim-Mail-From: m.tretter@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_LOW, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Fri, 06 Oct 2023 08:07:16 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779019122487356327 X-GMAIL-MSGID: 1779019122487356327 The PLL reference clock may change at runtime when its parent clock changes. For example, this may happen on the i.MX8M Nano if the reference clock is a child of the Video PLL. If the pixel clock changes, this may propagate to the Video PLL and as a side effect change the reference clock. Thus, reading the clock rate during probe is not sufficient to correctly configure the PLL for the expected hs clock. Read the actual rate of the reference clock before calculating the PLL configuration parameters. Note that the "samsung,pll-clock-frequency" is always preferred and PLL reference clock is only read from the clock tree if that device tree property is not set. Reviewed-by: Inki Dae Acked-by: Inki Dae Tested-by: Frieder Schrempf # Kontron BL i.MX8MM + Waveshare 10.1inch HDMI LCD (E) Reviewed-by: Marco Felsch Signed-off-by: Michael Tretter --- Changes in v2: - Clarify commit message --- drivers/gpu/drm/bridge/samsung-dsim.c | 16 +++++++++------- include/drm/bridge/samsung-dsim.h | 1 + 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index 3e8ee9d73a72..392c023c5925 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -612,7 +612,12 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi, u16 m; u32 reg; - fin = dsi->pll_clk_rate; + if (dsi->pll_clk) + fin = clk_get_rate(dsi->pll_clk); + else + fin = dsi->pll_clk_rate; + dev_dbg(dsi->dev, "PLL ref clock freq %lu\n", fin); + fout = samsung_dsim_pll_find_pms(dsi, fin, freq, &p, &m, &s); if (!fout) { dev_err(dsi->dev, @@ -1822,18 +1827,15 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi) u32 lane_polarities[5] = { 0 }; struct device_node *endpoint; int i, nr_lanes, ret; - struct clk *pll_clk; ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency", &dsi->pll_clk_rate, 1); /* If it doesn't exist, read it from the clock instead of failing */ if (ret < 0) { dev_dbg(dev, "Using sclk_mipi for pll clock frequency\n"); - pll_clk = devm_clk_get(dev, "sclk_mipi"); - if (!IS_ERR(pll_clk)) - dsi->pll_clk_rate = clk_get_rate(pll_clk); - else - return PTR_ERR(pll_clk); + dsi->pll_clk = devm_clk_get(dev, "sclk_mipi"); + if (IS_ERR(dsi->pll_clk)) + return PTR_ERR(dsi->pll_clk); } /* If it doesn't exist, use pixel clock instead of failing */ diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung-dsim.h index 05100e91ecb9..31ff88f152fb 100644 --- a/include/drm/bridge/samsung-dsim.h +++ b/include/drm/bridge/samsung-dsim.h @@ -87,6 +87,7 @@ struct samsung_dsim { void __iomem *reg_base; struct phy *phy; struct clk **clks; + struct clk *pll_clk; struct regulator_bulk_data supplies[2]; int irq; struct gpio_desc *te_gpio;