From patchwork Thu Aug 17 18:20:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andr=C3=A9_Almeida?= X-Patchwork-Id: 136042 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b82d:0:b0:3f2:4152:657d with SMTP id z13csp1551949vqi; Fri, 18 Aug 2023 10:10:54 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFfn19Teue1r6w8AmXhp7k7YAnv/yeQB/BVTFGRkm722OvjcyX39n2rHA2xPS2ETcVnDiiq X-Received: by 2002:a17:90a:6606:b0:26d:2158:10ac with SMTP id l6-20020a17090a660600b0026d215810acmr2903213pjj.14.1692378654088; Fri, 18 Aug 2023 10:10:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692378654; cv=none; d=google.com; s=arc-20160816; b=O2H0Kk+bhauU/hjo5nCHRgyIm95/vAMGdSViHqNc559fVDR0DPJQGTXJFGJmYvMw4V m3dRvS9l/GVmxMfPCkUiJIbnjIf6kXLn/AcCFq7yKbrG4NE1RaM8YNX8g0PxFgQbPzzB DD9jwIhKpWHn3B6MmHt5wSMQIe7Qcbs9EblgEpz+Ak21Pq6ZLKxAQ0T5WtqxKg1LOvGr jLfsBmQVNTSIoM2O/GhaBWaJBkNuF4OUmA/j2gMFep/sF9JFqOWvuc+E+2KU2H3qLwo5 /LAY6oSuA2UhADJPvXbpPMSi7ZmLJVAlik54hV/PV71vnYqdr3noYR6yXgZpFKWzjTgA vmwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=iUYe9g2MBePpeImYFZSYmc73rD01LVejX27ZWnGqtrg=; fh=akTS0Wq8jEms5e4CIjRZ2klQmCylMzrjhYuxow3r01E=; b=Mt2MIVX+/t9yce3+eKkVFIrq2jKFY77Qu8UHC8VXAgrdlZJtd0d/e9q+k81fEdKDFc 2h/fb5Qj2VXYSRepK47nTA/5iP3UuzpxcYkafBm6Ta/kTIqPYzJ/G0+BMyoS4GgEH1JH 3n5CH+9hdz0mZkLrhnhsEfdW4qQ1LLEzG91dev0jxprq4ddYawxPnIg8nuxmswOpzlgs 5qEgZbbVNildvpML54c4ipnyXepHz7PJHZyfpvgKoIJghhog/F8BD3RYwiwCLatzT6mF lmMt95NEI4wFo22h0Vl843wi+v4jsh7fNhgdEvlOlc0NgMZXl23DO0b8dLGptwCtKLOJ DBVw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=SY1uUsqW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id hk15-20020a17090b224f00b00263ba5d7088si3602654pjb.48.2023.08.18.10.10.39; Fri, 18 Aug 2023 10:10:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=SY1uUsqW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354384AbjHQSYJ (ORCPT + 99 others); Thu, 17 Aug 2023 14:24:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1354437AbjHQSXs (ORCPT ); Thu, 17 Aug 2023 14:23:48 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 835953AB4 for ; Thu, 17 Aug 2023 11:23:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=iUYe9g2MBePpeImYFZSYmc73rD01LVejX27ZWnGqtrg=; b=SY1uUsqWfuvjq6yENvUMBo1gqM SC9arx0L3MSypUGtfvK41ncQFrO1ADfv0LvGbu4HK1dVwBJ1Kc6bZlnSbkdqCPtR2Di6B/XbGDzjl pXSqqX8A5vcEvbEeqif571LDArSCs4OrivzcngH+koG87KNF0wHBzuZxPJCWMaZ4HOHP9Nu1djJ2p m2vdgMuNmDucHx6h6eBQ1yHnnculLgxon+8YriDf5zXs2h1M+sI9fZVnaF1aX/ampnTenit2fXOpB ceLV86A34+yv4MNCqIfzm2WFVvfEy9mYDxdxKlvWAn9ndgX8jaUAvbnC51D8my54bBD/RSDuEiZd4 FZtXpE/A==; Received: from [191.193.179.209] (helo=steammachine.lan) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1qWhcJ-0021I9-BT; Thu, 17 Aug 2023 20:21:07 +0200 From: =?utf-8?q?Andr=C3=A9_Almeida?= To: dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: kernel-dev@igalia.com, alexander.deucher@amd.com, christian.koenig@amd.com, pierre-eric.pelloux-prayer@amd.com, =?utf-8?b?J01hcmVrIE9sxaHDoWsn?= , Samuel Pitoiset , Bas Nieuwenhuizen , =?utf-8?q?Timur_Krist=C3=B3f?= , Shashank Sharma , =?utf-8?q?Andr=C3=A9_Almeida?= Subject: [PATCH v5 3/5] drm/amdgpu: Encapsulate all device reset info Date: Thu, 17 Aug 2023 15:20:48 -0300 Message-ID: <20230817182050.205925-4-andrealmeid@igalia.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230817182050.205925-1-andrealmeid@igalia.com> References: <20230817182050.205925-1-andrealmeid@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774587639670846547 X-GMAIL-MSGID: 1774587639670846547 To better organize struct amdgpu_device, keep all reset information related fields together in a separated struct. Signed-off-by: André Almeida --- v5: new patch, as requested by Shashank Sharma --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 34 +++++++++++++-------- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 10 +++--- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 16 +++++----- 3 files changed, 34 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 0d560b713948..56d78ca6e917 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -781,6 +781,26 @@ struct amdgpu_mqd { #define AMDGPU_PRODUCT_NAME_LEN 64 struct amdgpu_reset_domain; +#ifdef CONFIG_DEV_COREDUMP +struct amdgpu_coredump_info { + struct amdgpu_device *adev; + struct amdgpu_task_info reset_task_info; + struct timespec64 reset_time; + bool reset_vram_lost; +}; +#endif + +struct amdgpu_reset_info { + /* reset dump register */ + u32 *reset_dump_reg_list; + u32 *reset_dump_reg_value; + int num_regs; + +#ifdef CONFIG_DEV_COREDUMP + struct amdgpu_coredump_info *coredump_info; +#endif +}; + /* * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise. */ @@ -1084,10 +1104,7 @@ struct amdgpu_device { struct mutex benchmark_mutex; - /* reset dump register */ - uint32_t *reset_dump_reg_list; - uint32_t *reset_dump_reg_value; - int num_regs; + struct amdgpu_reset_info reset_info; bool scpm_enabled; uint32_t scpm_status; @@ -1100,15 +1117,6 @@ struct amdgpu_device { uint32_t aid_mask; }; -#ifdef CONFIG_DEV_COREDUMP -struct amdgpu_coredump_info { - struct amdgpu_device *adev; - struct amdgpu_task_info reset_task_info; - struct timespec64 reset_time; - bool reset_vram_lost; -}; -#endif - static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) { return container_of(ddev, struct amdgpu_device, ddev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index a4faea4fa0b5..3136a0774dd9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -2016,8 +2016,8 @@ static ssize_t amdgpu_reset_dump_register_list_read(struct file *f, if (ret) return ret; - for (i = 0; i < adev->num_regs; i++) { - sprintf(reg_offset, "0x%x\n", adev->reset_dump_reg_list[i]); + for (i = 0; i < adev->reset_info.num_regs; i++) { + sprintf(reg_offset, "0x%x\n", adev->reset_info.reset_dump_reg_list[i]); up_read(&adev->reset_domain->sem); if (copy_to_user(buf + len, reg_offset, strlen(reg_offset))) return -EFAULT; @@ -2074,9 +2074,9 @@ static ssize_t amdgpu_reset_dump_register_list_write(struct file *f, if (ret) goto error_free; - swap(adev->reset_dump_reg_list, tmp); - swap(adev->reset_dump_reg_value, new); - adev->num_regs = i; + swap(adev->reset_info.reset_dump_reg_list, tmp); + swap(adev->reset_info.reset_dump_reg_value, new); + adev->reset_info.num_regs = i; up_write(&adev->reset_domain->sem); ret = size; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index b5b879bcc5c9..96975591841d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4790,10 +4790,10 @@ static int amdgpu_reset_reg_dumps(struct amdgpu_device *adev) lockdep_assert_held(&adev->reset_domain->sem); - for (i = 0; i < adev->num_regs; i++) { - adev->reset_dump_reg_value[i] = RREG32(adev->reset_dump_reg_list[i]); - trace_amdgpu_reset_reg_dumps(adev->reset_dump_reg_list[i], - adev->reset_dump_reg_value[i]); + for (i = 0; i < adev->reset_info.num_regs; i++) { + adev->reset_info.reset_dump_reg_value[i] = RREG32(adev->reset_info.reset_dump_reg_list[i]); + trace_amdgpu_reset_reg_dumps(adev->reset_info.reset_dump_reg_list[i], + adev->reset_info.reset_dump_reg_value[i]); } return 0; @@ -4831,13 +4831,13 @@ static ssize_t amdgpu_devcoredump_read(char *buffer, loff_t offset, if (coredump->reset_vram_lost) drm_printf(&p, "VRAM is lost due to GPU reset!\n"); - if (coredump->adev->num_regs) { + if (coredump->adev->reset_info.num_regs) { drm_printf(&p, "AMDGPU register dumps:\nOffset: Value:\n"); - for (i = 0; i < coredump->adev->num_regs; i++) + for (i = 0; i < coredump->adev->reset_info.num_regs; i++) drm_printf(&p, "0x%08x: 0x%08x\n", - coredump->adev->reset_dump_reg_list[i], - coredump->adev->reset_dump_reg_value[i]); + coredump->adev->reset_info.reset_dump_reg_list[i], + coredump->adev->reset_info.reset_dump_reg_value[i]); } return count - iter.remain;