| Message ID | 20230814141007.3721197-8-bryan.odonoghue@linaro.org |
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From: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
To: rfoss@kernel.org, todor.too@gmail.com, bryan.odonoghue@linaro.org,
agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org,
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Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org, stable@vger.kernel.org
Subject: [PATCH v0 7/9] media: qcom: camss: Fix invalid clock enable bit
disjunction
Date: Mon, 14 Aug 2023 15:10:05 +0100
Message-ID: <20230814141007.3721197-8-bryan.odonoghue@linaro.org>
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| Series |
media: qcom: camss: Bugfix series
|
|
Commit Message
Bryan O'Donoghue
Aug. 14, 2023, 2:10 p.m. UTC
define CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE BIT(7)
disjunction for gen2 ? BIT(7) : is a nop we are setting the same bit
either way.
Fixes: 4abb21309fda ("media: camss: csiphy: Move to hardcode CSI Clock Lane number")
Cc: stable@vger.kernel.org
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index 04baa80494c66..4dba61b8d3f2a 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -476,7 +476,7 @@ static void csiphy_lanes_enable(struct csiphy_device *csiphy, settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate); - val = is_gen2 ? BIT(7) : CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; + val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE; for (i = 0; i < c->num_data; i++) val |= BIT(c->data[i].pos * 2);