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[2620:137:e000::1:20]) by mx.google.com with ESMTP id u8-20020a17090341c800b001bba879700fsi3691341ple.514.2023.08.11.09.27.53; Fri, 11 Aug 2023 09:28:07 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=R251VmnE; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235993AbjHKPRM (ORCPT + 99 others); Fri, 11 Aug 2023 11:17:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45956 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235945AbjHKPRK (ORCPT ); Fri, 11 Aug 2023 11:17:10 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0A87730C4; Fri, 11 Aug 2023 08:17:03 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 37BFGud2023129; Fri, 11 Aug 2023 10:16:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691767016; bh=HaSWg1bDEQd9Lgc9+eEm2PgF4DqPPgwHMlnRBZAtlJU=; h=From:To:Subject:Date:In-Reply-To:References; b=R251VmnEqGezLlz7tS3z7RQGjE8U7LMCu1p2qf9Ch0qXJJAaeb2eEwVB7p6UmxYnI eKZbppxvQ/PU1we8RblIDAogNZSPyOFS0Qx7iNFqwespyZ/V3G8VSoyXu8CSD0scbk OjmPrSyWe3ba6vklgTpTTNDoeKN0WXSHQnpJzsqk= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 37BFGu5C007500 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 11 Aug 2023 10:16:56 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 11 Aug 2023 10:16:55 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 11 Aug 2023 10:16:55 -0500 Received: from TI.dhcp.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 37BFGice121323; Fri, 11 Aug 2023 10:16:52 -0500 From: Apurva Nandan To: Apurva Nandan , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Udit Kumar , Hari Nagalla , Dasnavis Sabiya Subject: [PATCH v4 2/3] arm64: dts: ti: k3-j784s4-evm: Add phase tags marking Date: Fri, 11 Aug 2023 20:46:43 +0530 Message-ID: <20230811151644.3216621-3-a-nandan@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230811151644.3216621-1-a-nandan@ti.com> References: <20230811151644.3216621-1-a-nandan@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_PASS,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773950769830630329 X-GMAIL-MSGID: 1773950769830630329 bootph-all as phase tag was added to dt-schema (dtschema/schemas/bootph.yaml) to cover U-Boot challenges with DT. That's why add it also to Linux to be aligned with bootloader requirement. wkup_uart0, wkup_i2c0, mcu_uart0, main_uart8, fss, ospi0, ospi1, main_sdhci0 and main_sdhci1 are required for bootloader operation on TI K3 J784S4 EVM. These IPs along with pinmuxes need to be marked for all bootloader phases, hence add bootph-all to these nodes in kernel dts. Signed-off-by: Apurva Nandan --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index edc1009b2d1e..47d41d60e49a 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -252,7 +252,9 @@ vdd_sd_dv: regulator-TLV71033 { }; &main_pmx0 { + bootph-all; main_uart8_pins_default: main-uart8-default-pins { + bootph-all; pinctrl-single,pins = < J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */ @@ -269,6 +271,7 @@ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ }; main_mmc1_pins_default: main-mmc1-default-pins { + bootph-all; pinctrl-single,pins = < J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ @@ -289,7 +292,9 @@ J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ }; &wkup_pmx2 { + bootph-all; wkup_uart0_pins_default: wkup-uart0-default-pins { + bootph-all; pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ @@ -299,6 +304,7 @@ J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */ }; wkup_i2c0_pins_default: wkup-i2c0-default-pins { + bootph-all; pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ @@ -306,6 +312,7 @@ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ }; mcu_uart0_pins_default: mcu-uart0-default-pins { + bootph-all; pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0_CTSn */ J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART0_RTSn */ @@ -366,7 +373,9 @@ J784S4_WKUP_IOPAD(0x170, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ }; &wkup_pmx0 { + bootph-all; mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { + bootph-all; pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ @@ -384,7 +393,9 @@ J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ }; &wkup_pmx1 { + bootph-all; mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins { + bootph-all; pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x004, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_ECC_FAIL */ J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_RESET_OUT0 */ @@ -392,6 +403,7 @@ J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_RESET_OUT0 */ }; mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { + bootph-all; pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ @@ -406,6 +418,7 @@ J784S4_WKUP_IOPAD(0x00C, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ }; &wkup_uart0 { + bootph-all; /* Firmware usage */ status = "reserved"; pinctrl-names = "default"; @@ -413,6 +426,7 @@ &wkup_uart0 { }; &wkup_i2c0 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&wkup_i2c0_pins_default>; @@ -426,12 +440,14 @@ eeprom@50 { }; &mcu_uart0 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_uart0_pins_default>; }; &main_uart8 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart8_pins_default>; @@ -442,15 +458,18 @@ &ufs_wrapper { }; &fss { + bootph-all; status = "okay"; }; &ospi0 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_default>; flash@0 { + bootph-all; compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <8>; @@ -498,6 +517,7 @@ partition@800000 { }; partition@3fc0000 { + bootph-all; label = "ospi.phypattern"; reg = <0x3fc0000 0x40000>; }; @@ -506,11 +526,13 @@ partition@3fc0000 { }; &ospi1 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; flash@0 { + bootph-all; compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <1>; @@ -558,6 +580,7 @@ partition@800000 { }; partition@3fc0000 { + bootph-all; label = "qspi.phypattern"; reg = <0x3fc0000 0x40000>; }; @@ -602,6 +625,7 @@ exp2: gpio@22 { }; &main_sdhci0 { + bootph-all; /* eMMC */ status = "okay"; non-removable; @@ -610,6 +634,7 @@ &main_sdhci0 { }; &main_sdhci1 { + bootph-all; /* SD card */ status = "okay"; pinctrl-0 = <&main_mmc1_pins_default>;