From patchwork Fri Aug 11 03:45:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anshuman Khandual X-Patchwork-Id: 134317 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp857251vqi; Thu, 10 Aug 2023 21:53:10 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGG5K9mbBFY7xBj5RZVR/lGWkgS8dI42zMeZqyxB3G6zu26Gn4ZHebjXHrHp/7JTqxYcP0m X-Received: by 2002:a17:902:e805:b0:1bc:283:75a8 with SMTP id u5-20020a170902e80500b001bc028375a8mr1079160plg.26.1691729589756; Thu, 10 Aug 2023 21:53:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691729589; cv=none; d=google.com; s=arc-20160816; b=fE+GrXpt7LfWQFzF5ezcsIIEsmUk8TH0PpfvODlnIKbo1XMXOgaOLOEWrFO0jNLJwX kvuhU+Ovvrtxs2OUP5yDvBIp4hDbjGhv8l5gUfOBEGnbJFuCn9+WMIrqYmv6Dac3glBE I82sKA18mybqJjELkMs5shoQIjTtGiQIGJMnyKdsT8UHsCRKorlyBKBQ2inEGNSkdov7 3qpuY5dJ5zki+d6glpTl8oOW6rFM3KfqvRtMNOXRDByhdfUrFTQ1mK1N9I2Gosr/ms5E ffCEQWevbWNlJUDdiIOtSjjHg0r0yWT4WiTDiEWns2zCc1m6h8j5prI42JxwNBlovrzS wqpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=FIoZvWA3+wmZBYrw5riGZgIlrjQ+g/EaxF2VT+KS3VU=; fh=i7k4OkcaLUFocIK64fg5M0UL6Z7MqFc0/WYsE6IUDvI=; b=aNPn1YCCeZAUgBbrkPotIzjEXx6xfFb0yWbAwbMvLroO5uqHSksbRUFIqmnj0WZKvK mbp5SQd+Oqul9EgCZHad2X9BfL8v7SbeNcf4SmdxusyDJ5Cvx44KQtN+u5L6trjY+6oy cKVCYVTWzSMBQGJ7pGv9pqOe0DN2MScGMHt/c15gMGilAHx8BZYmGgtxPk2RNfzgVLnP H3ZHr/bLDOaXPZZWF+njzAmuGy9kCGRSbZydPdj9OO22ri6g21hOSV5RFmGCag/BLsX9 0Emle8/KIkHo7G+jB1hTMstFIq6tPKfQEBm+cCuauF25+Qouvk3/+dL628oZyiSLdClS idYA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id r10-20020a170902be0a00b001bc5f13c67esi2614276pls.589.2023.08.10.21.52.55; Thu, 10 Aug 2023 21:53:09 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232953AbjHKDq0 (ORCPT + 99 others); Thu, 10 Aug 2023 23:46:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58626 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233266AbjHKDqW (ORCPT ); Thu, 10 Aug 2023 23:46:22 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id A2EAC2D78; Thu, 10 Aug 2023 20:46:21 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B61C5D75; Thu, 10 Aug 2023 20:47:03 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.54.13]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D6E0E3F6C4; Thu, 10 Aug 2023 20:46:16 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, suzuki.poulose@arm.com Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Mike Leach , James Clark , Leo Yan , Jonathan Corbet , linux-doc@vger.kernel.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Subject: [PATCH V3 2/3] coresight: etm: Make cycle count threshold user configurable Date: Fri, 11 Aug 2023 09:15:59 +0530 Message-Id: <20230811034600.944386-3-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811034600.944386-1-anshuman.khandual@arm.com> References: <20230811034600.944386-1-anshuman.khandual@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773904673775359955 X-GMAIL-MSGID: 1773907045962533665 Cycle counting is enabled, when requested and supported but with a default threshold value ETM_CYC_THRESHOLD_DEFAULT i.e 0x100 getting into TRCCCCTLR, representing the minimum interval between cycle count trace packets. This makes cycle threshold user configurable, from the user space via perf event attributes. Although it falls back using ETM_CYC_THRESHOLD_DEFAULT, in case no explicit request. As expected it creates a sysfs file as well. /sys/bus/event_source/devices/cs_etm/format/cc_threshold New 'cc_threshold' uses 'event->attr.config3' as no more space is available in 'event->attr.config1' or 'event->attr.config2'. Cc: Suzuki K Poulose Cc: Mike Leach Cc: James Clark Cc: Leo Yan Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual Reviewed-by: Mike Leach --- drivers/hwtracing/coresight/coresight-etm-perf.c | 2 ++ drivers/hwtracing/coresight/coresight-etm4x-core.c | 12 ++++++++++-- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 5ca6278baff4..09f75dffae60 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -68,6 +68,7 @@ PMU_FORMAT_ATTR(preset, "config:0-3"); PMU_FORMAT_ATTR(sinkid, "config2:0-31"); /* config ID - set if a system configuration is selected */ PMU_FORMAT_ATTR(configid, "config2:32-63"); +PMU_FORMAT_ATTR(cc_threshold, "config3:0-11"); /* @@ -101,6 +102,7 @@ static struct attribute *etm_config_formats_attr[] = { &format_attr_preset.attr, &format_attr_configid.attr, &format_attr_branch_broadcast.attr, + &format_attr_cc_threshold.attr, NULL, }; diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 1f3d29a639ff..ad28ee044cba 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -644,7 +644,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev, struct etmv4_config *config = &drvdata->config; struct perf_event_attr *attr = &event->attr; unsigned long cfg_hash; - int preset; + int preset, cc_threshold; /* Clear configuration from previous run */ memset(config, 0, sizeof(struct etmv4_config)); @@ -667,7 +667,15 @@ static int etm4_parse_event_config(struct coresight_device *csdev, if (attr->config & BIT(ETM_OPT_CYCACC)) { config->cfg |= TRCCONFIGR_CCI; /* TRM: Must program this for cycacc to work */ - config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT; + cc_threshold = attr->config3 & ETM_CYC_THRESHOLD_MASK; + if (cc_threshold) { + if (cc_threshold < drvdata->ccitmin) + config->ccctlr = drvdata->ccitmin; + else + config->ccctlr = cc_threshold; + } else { + config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT; + } } if (attr->config & BIT(ETM_OPT_TS)) { /*