From patchwork Thu Aug 10 16:03:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 134098 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp542541vqi; Thu, 10 Aug 2023 09:37:02 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGofrZ9fQGCl1dFlofkvpZ220liitY7f4W/tKik7qgrFHUnIYeS4i2ULLD3XL4SAXD40qn6 X-Received: by 2002:a05:6a20:1055:b0:13a:59b1:c88b with SMTP id gt21-20020a056a20105500b0013a59b1c88bmr2729977pzc.45.1691685422106; Thu, 10 Aug 2023 09:37:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691685422; cv=none; d=google.com; s=arc-20160816; b=TSrR5X9gsL28MU0o1m8TGf7qlYKpKk2Xf0z9GEdl9iWQZ9RW+VJFub1EoN+KeYLEGm sAdPLC7cKdyujpBiCciQykxfQm2ckezl2seoOYQgtXcwuf+qo0cy0KiaLsOq5c03s6g2 KZ7m9J5geUtCkkt3V8pvXMNYh3cyi86miDwiNAE3yNaDQ4UM6BziT3/15VrIGy2Jc2kz VawWL2PW9TU5C1TdwW1Ilk0oy3h5GupimEZ2UkHiDI4Y44TDd3agIAVBkEbita1EE+PH 4rVZ07E1b9+CJdgpYDPLjJeDgUbxfvb9PBw5IX630niE4KMCk9zhnTkRATjl2VVGXWvu RgNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=uzsQHbRviTfC2VrePHl/yc6/PBLmqDaXFQ9Hnya6Dwk=; fh=K4g2hpcHeis9i+u86e9V+yTBU0PZFkfdrKenkMdV+qw=; b=wQKlrXexoiBLa5swa7bJ4Vgmq5MfkjNGQUfPIh6x30FtSzWfBH/N4J6kqAyipQnN10 F2tpagAs3l/t6OzgQgorCJrw3p9VSRaHal3iGkIPKJO71nvrSg50EPV4PMIpdI1CzbJc tVgjIJykXy212zpdd7s/J/hIJaN/iszD14bCkXU8q7AO16ah8rlFn7NQ26ZdhG4qBzS5 k+SevkMX1k5r32c2jk1YX5QNMxjN7TdUw/ITz/a71QcM1skZATQxkI4v9EbyC/kZLad4 /Z1G1LfmCzPZP65WbeZBFt/7YEcTYDzuxsUzrSgAz4vfaauqwAI/P5CMl1O5wO1sJbuk IGSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=Wwl0DnwM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id h64-20020a636c43000000b00565642feaa4si797926pgc.172.2023.08.10.09.36.48; Thu, 10 Aug 2023 09:37:02 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=Wwl0DnwM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236477AbjHJQFA (ORCPT + 99 others); Thu, 10 Aug 2023 12:05:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236465AbjHJQEN (ORCPT ); Thu, 10 Aug 2023 12:04:13 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 458B12D79 for ; Thu, 10 Aug 2023 09:04:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=uzsQHbRviTfC2VrePHl/yc6/PBLmqDaXFQ9Hnya6Dwk=; b=Wwl0DnwMAO/zAXwX/PdTSmn7Pq pqT6lkNOeVzsnlEu9d70NrsjBwDCpf6nh+jSqIlR8tvvQixUnUV2Ie0tDhcnntBgvowAl6sb+VKKq DRmZbTnDncI/5/UL5m3NQ3BW03hbSpT/IMsG6nr9kPT3LyVVn6aU2CDjhry/T9DCqFEskEjjtsmGg j769SsigLKm6K9qhmnToQffo5y16g6+8dDzCH/bfxZRJRZKfty/X11st5Ea/maA0FJ1X1KRhmHdk0 7ELq+ih98usBx2tUUpQCmIVgEJBsCfSbNzRNLyjrYeOeWVcuTB2iHEtmSLUKcj4s5Wz0bwXp50Fye SwDm3FfA==; Received: from [38.44.68.151] (helo=killbill.home) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1qU88n-00GjYD-F9; Thu, 10 Aug 2023 18:04:01 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Pekka Paalanen , Simon Ser , kernel-dev@igalia.com, linux-kernel@vger.kernel.org Subject: [PATCH v2 20/34] drm/amd/display: add plane degamma TF and LUT support Date: Thu, 10 Aug 2023 15:03:00 -0100 Message-Id: <20230810160314.48225-21-mwen@igalia.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230810160314.48225-1-mwen@igalia.com> References: <20230810160314.48225-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773860733199342337 X-GMAIL-MSGID: 1773860733199342337 From: Joshua Ashton Set DC plane with user degamma LUT or predefined TF from driver-specific plane color properties. If plane and CRTC degamma are set in the same time, plane degamma has priority. That means, we only set CRTC degamma if we don't have plane degamma LUT or TF to configure. We return -EINVAL if we don't have plane degamma settings, so we can continue and check CRTC degamma. Reviewed-by: Harry Wentland Signed-off-by: Joshua Ashton Signed-off-by: Melissa Wen --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 + .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 70 +++++++++++++++++-- 3 files changed, 69 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 78fdd0b95ae8..3e5aa1e46662 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5009,7 +5009,9 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev, * Always set input transfer function, since plane state is refreshed * every time. */ - ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state); + ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, + plane_state, + dc_plane_state); if (ret) return ret; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 51471675c298..23e3984f17fb 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -903,6 +903,7 @@ int amdgpu_dm_create_color_properties(struct amdgpu_device *adev); int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state); int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, + struct drm_plane_state *plane_state, struct dc_plane_state *dc_plane_state); void amdgpu_dm_update_connector_after_detect( diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 74eb02655d96..d019a091b08e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -843,9 +843,58 @@ map_crtc_degamma_to_dc_plane(struct dm_crtc_state *crtc, return 0; } +static int +__set_dm_plane_degamma(struct drm_plane_state *plane_state, + struct dc_plane_state *dc_plane_state) +{ + struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state); + const struct drm_color_lut *degamma_lut; + enum amdgpu_transfer_function tf = AMDGPU_TRANSFER_FUNCTION_DEFAULT; + uint32_t degamma_size; + bool has_degamma_lut; + int ret; + + degamma_lut = __extract_blob_lut(dm_plane_state->degamma_lut, + °amma_size); + + has_degamma_lut = degamma_lut && + !__is_lut_linear(degamma_lut, degamma_size); + + tf = dm_plane_state->degamma_tf; + + /* If we don't have plane degamma LUT nor TF to set on DC, we have + * nothing to do here, return. + */ + if (!has_degamma_lut && tf == AMDGPU_TRANSFER_FUNCTION_DEFAULT) + return -EINVAL; + + dc_plane_state->in_transfer_func->tf = amdgpu_tf_to_dc_tf(tf); + + if (has_degamma_lut) { + ASSERT(degamma_size == MAX_COLOR_LUT_ENTRIES); + + dc_plane_state->in_transfer_func->type = + TF_TYPE_DISTRIBUTED_POINTS; + + ret = __set_input_tf(dc_plane_state->in_transfer_func, + degamma_lut, degamma_size); + if (ret) + return ret; + } else { + dc_plane_state->in_transfer_func->type = + TF_TYPE_PREDEFINED; + + if (!mod_color_calculate_degamma_params(NULL, + dc_plane_state->in_transfer_func, NULL, false)) + return -ENOMEM; + } + return 0; +} + /** * amdgpu_dm_update_plane_color_mgmt: Maps DRM color management to DC plane. * @crtc: amdgpu_dm crtc state + * @plane_state: DRM plane state * @dc_plane_state: target DC surface * * Update the underlying dc_stream_state's input transfer function (ITF) in @@ -856,13 +905,28 @@ map_crtc_degamma_to_dc_plane(struct dm_crtc_state *crtc, * 0 on success. -ENOMEM if mem allocation fails. */ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, + struct drm_plane_state *plane_state, struct dc_plane_state *dc_plane_state) { bool has_crtc_cm_degamma; int ret; + /* Initially, we can just bypass the DGM block. */ + dc_plane_state->in_transfer_func->type = TF_TYPE_BYPASS; + dc_plane_state->in_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; + + /* After, we start to update values according to color props */ has_crtc_cm_degamma = (crtc->cm_has_degamma || crtc->cm_is_degamma_srgb); - if (has_crtc_cm_degamma){ + + ret = __set_dm_plane_degamma(plane_state, dc_plane_state); + if (ret != -EINVAL) + return ret; + + /* If we are here, it means we don't have plane degamma settings, check + * if we have CRTC degamma waiting for mapping to pre-blending degamma + * block + */ + if (has_crtc_cm_degamma) { /* AMD HW doesn't have post-blending degamma caps. When DRM * CRTC atomic degamma is set, we maps it to DPP degamma block * (pre-blending) or, on legacy gamma, we use DPP degamma to @@ -872,10 +936,6 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, ret = map_crtc_degamma_to_dc_plane(crtc, dc_plane_state); if (ret) return ret; - } else { - /* ...Otherwise we can just bypass the DGM block. */ - dc_plane_state->in_transfer_func->type = TF_TYPE_BYPASS; - dc_plane_state->in_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; } return 0;