From patchwork Thu Aug 10 16:02:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melissa Wen X-Patchwork-Id: 134078 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b824:0:b0:3f2:4152:657d with SMTP id z4csp533393vqi; Thu, 10 Aug 2023 09:21:51 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFwVK7hMuAt9oXqpMdkmAhtHlbSUPuFsV/UYrexmweDJRe87J8SY41++c4/7f8vQBoKRE5c X-Received: by 2002:a05:6a20:d426:b0:127:76ab:a707 with SMTP id il38-20020a056a20d42600b0012776aba707mr2303579pzb.30.1691684511026; Thu, 10 Aug 2023 09:21:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691684511; cv=none; d=google.com; s=arc-20160816; b=v5edX0toxkb/1uGoqB2Tw0K5AHmkxE2YLjxuFvLlXP5Q+RkX7STFptRKur+Zh9zQXm 3kenhi4odOIB4iYWuU6hCWE/CWuMM6TdTj/pnZZfEsAiMWYOOJBSs0nbsATomJa9wfq3 YC+9mEAI0Ox/7ouY/K/5S6CfCbPboKs5Yj9pwF8eKbNMzkA6fFt2j/0MGLEsKS7dBoO8 5MX44iiz8o60X94TiotorJhNKFFynvQCMV2rKOdeslo4fzsDGyGFwY/OZQPv6JyCIhcp uQsCaWpyywpBF3KBp29jSNZDu8UOlttLGoMH2H+0ZP5+9M4FWgYNljdI9X25va5WhBnC 6yNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=7h7yLqPjcU15/dvMrBp46UZ6Z5mMwdlomOvGnBFHL1M=; fh=K4g2hpcHeis9i+u86e9V+yTBU0PZFkfdrKenkMdV+qw=; b=klVfXvTyM4dioy0OBaUpcyZyIpT3Ft3mV7GHCiJqZoXAofpFAep23jSbtoCiBYKpP6 tXcX9TZV2vSmle3gIjwYJS0TAgVCdElVpbqF0vZtRH2mkUM3OIWdiloSlHWLfW9sCZjb QrHJQPSU7u/MhWPHDnUT6JVD8ao4nsEMsbIqulDHxpeed0eMuIFzJo4dTN+OdoamnimW nplwYmx52USwzrZWFDqCp5jTsXEphCAfR4mf67bE5wGlGWrYLbB8vz58nhXaF/YHLL18 7OB+o5/lLjnNQTY1NvJpzdSZj6089Nlk4AR6UY6/4wNPDrv3tlMOynDYVC7j+9US8x1r KDZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=QKGFhxmj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id t7-20020a056a0021c700b0068719ad3172si1855470pfj.76.2023.08.10.09.21.34; Thu, 10 Aug 2023 09:21:51 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@igalia.com header.s=20170329 header.b=QKGFhxmj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236571AbjHJQEo (ORCPT + 99 others); Thu, 10 Aug 2023 12:04:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54928 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236382AbjHJQEE (ORCPT ); Thu, 10 Aug 2023 12:04:04 -0400 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E1FB02108 for ; Thu, 10 Aug 2023 09:04:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=7h7yLqPjcU15/dvMrBp46UZ6Z5mMwdlomOvGnBFHL1M=; b=QKGFhxmjFSg4/aU9D/aH31uFaY IL6EExJybvKqUE/oSrEXus6XIUMmM6T7GZlLjL6uTvHXcuG/LvjAE5jWZkk9CxeDY5W/gmih0uWAW nFKe0Pkl1Sxc5NJq+HXauoJRYrkd+uSGeZH3rrpvQzB/bviIyVyAcpPJifQeKhdqBuH8ot/PfpPPs 0vp6aXXiyXpyZwtF7TnFm43T3p6hMwDlnAKHaLxgcCATfh0P/ZUul14HCT/lIfYqSOaDTYHm1VXm+ HAgHkBoyGPe2ofsUTH4dZfHb/sosbZ6slQUWKUmKsod2VYAjoYQrI3KqKfpTyV4xyom3qkqLCWpOe a3EeDV0A==; Received: from [38.44.68.151] (helo=killbill.home) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim) id 1qU88e-00GjYD-QU; Thu, 10 Aug 2023 18:03:52 +0200 From: Melissa Wen To: amd-gfx@lists.freedesktop.org, Harry Wentland , Rodrigo Siqueira , sunpeng.li@amd.com, Alex Deucher , dri-devel@lists.freedesktop.org, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: Joshua Ashton , Sebastian Wick , Xaver Hugl , Shashank Sharma , Nicholas Kazlauskas , sungjoon.kim@amd.com, Alex Hung , Pekka Paalanen , Simon Ser , kernel-dev@igalia.com, linux-kernel@vger.kernel.org Subject: [PATCH v2 16/34] drm/amd/display: add CRTC gamma TF support Date: Thu, 10 Aug 2023 15:02:56 -0100 Message-Id: <20230810160314.48225-17-mwen@igalia.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230810160314.48225-1-mwen@igalia.com> References: <20230810160314.48225-1-mwen@igalia.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773859777517709968 X-GMAIL-MSGID: 1773859777517709968 From: Joshua Ashton Add predefined transfer function programming. There is no pre-blending out gamma ROM, but we can use AMD color modules to program LUT parameters from a pre-defined TF and an empty regamma LUT (or bump up LUT parameters with pre-defined TF setup). v2: - update crtc color mgmt if regamma TF differs between states (Joshua) - map inverse EOTF to DC transfer function (Melissa) Signed-off-by: Joshua Ashton Co-developed-by: Melissa Wen Signed-off-by: Melissa Wen --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 + .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 73 +++++++++++++++---- 2 files changed, 58 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 77b4d671a9e0..272974b88cda 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -9456,6 +9456,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, * when a modeset is needed, to ensure it gets reprogrammed. */ if (dm_new_crtc_state->base.color_mgmt_changed || + dm_old_crtc_state->regamma_tf != dm_new_crtc_state->regamma_tf || drm_atomic_crtc_needs_modeset(new_crtc_state)) { ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); if (ret) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index c0bf55416b4d..0188e82d1fdd 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -468,16 +468,18 @@ static int __set_output_tf(struct dc_transfer_func *func, struct calculate_buffer cal_buffer = {0}; bool res; - ASSERT(lut && lut_size == MAX_COLOR_LUT_ENTRIES); - cal_buffer.buffer_index = -1; - gamma = dc_create_gamma(); - if (!gamma) - return -ENOMEM; + if (lut_size) { + ASSERT(lut && lut_size == MAX_COLOR_LUT_ENTRIES); - gamma->num_entries = lut_size; - __drm_lut_to_dc_gamma(lut, gamma, false); + gamma = dc_create_gamma(); + if (!gamma) + return -ENOMEM; + + gamma->num_entries = lut_size; + __drm_lut_to_dc_gamma(lut, gamma, false); + } if (func->tf == TRANSFER_FUNCTION_LINEAR) { /* @@ -485,32 +487,36 @@ static int __set_output_tf(struct dc_transfer_func *func, * on top of a linear input. But degamma params can be used * instead to simulate this. */ - gamma->type = GAMMA_CUSTOM; + if (gamma) + gamma->type = GAMMA_CUSTOM; res = mod_color_calculate_degamma_params(NULL, func, - gamma, true); + gamma, gamma != NULL); } else { /* * Assume sRGB. The actual mapping will depend on whether the * input was legacy or not. */ - gamma->type = GAMMA_CS_TFM_1D; - res = mod_color_calculate_regamma_params(func, gamma, false, + if (gamma) + gamma->type = GAMMA_CS_TFM_1D; + res = mod_color_calculate_regamma_params(func, gamma, gamma != NULL, has_rom, NULL, &cal_buffer); } - dc_gamma_release(&gamma); + if (gamma) + dc_gamma_release(&gamma); return res ? 0 : -ENOMEM; } static int amdgpu_dm_set_atomic_regamma(struct dc_stream_state *stream, const struct drm_color_lut *regamma_lut, - uint32_t regamma_size, bool has_rom) + uint32_t regamma_size, bool has_rom, + enum dc_transfer_func_predefined tf) { struct dc_transfer_func *out_tf = stream->out_transfer_func; int ret = 0; - if (regamma_size) { + if (regamma_size || tf != TRANSFER_FUNCTION_LINEAR) { /* CRTC RGM goes into RGM LUT. * * Note: there is no implicit sRGB regamma here. We are using @@ -518,7 +524,7 @@ static int amdgpu_dm_set_atomic_regamma(struct dc_stream_state *stream, * from a linear base. */ out_tf->type = TF_TYPE_DISTRIBUTED_POINTS; - out_tf->tf = TRANSFER_FUNCTION_LINEAR; + out_tf->tf = tf; ret = __set_output_tf(out_tf, regamma_lut, regamma_size, has_rom); } else { @@ -564,6 +570,38 @@ static int __set_input_tf(struct dc_transfer_func *func, return res ? 0 : -ENOMEM; } +static enum dc_transfer_func_predefined +amdgpu_tf_to_dc_tf(enum amdgpu_transfer_function tf) +{ + switch (tf) + { + default: + case AMDGPU_TRANSFER_FUNCTION_DEFAULT: + case AMDGPU_TRANSFER_FUNCTION_LINEAR: + return TRANSFER_FUNCTION_LINEAR; + case AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF: + case AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF: + return TRANSFER_FUNCTION_SRGB; + case AMDGPU_TRANSFER_FUNCTION_BT709_EOTF: + case AMDGPU_TRANSFER_FUNCTION_BT709_INV_EOTF: + return TRANSFER_FUNCTION_BT709; + case AMDGPU_TRANSFER_FUNCTION_PQ_EOTF: + case AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF: + return TRANSFER_FUNCTION_PQ; + case AMDGPU_TRANSFER_FUNCTION_UNITY: + return TRANSFER_FUNCTION_UNITY; + case AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF: + case AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF: + return TRANSFER_FUNCTION_GAMMA22; + case AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF: + case AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF: + return TRANSFER_FUNCTION_GAMMA24; + case AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF: + case AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF: + return TRANSFER_FUNCTION_GAMMA26; + } +} + /** * amdgpu_dm_verify_lut_sizes - verifies if DRM luts match the hw supported sizes * @crtc_state: the DRM CRTC state @@ -631,9 +669,12 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) const struct drm_color_lut *degamma_lut, *regamma_lut; uint32_t degamma_size, regamma_size; bool has_regamma, has_degamma; + enum dc_transfer_func_predefined tf = TRANSFER_FUNCTION_LINEAR; bool is_legacy; int r; + tf = amdgpu_tf_to_dc_tf(crtc->regamma_tf); + r = amdgpu_dm_verify_lut_sizes(&crtc->base); if (r) return r; @@ -683,7 +724,7 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) } else { regamma_size = has_regamma ? regamma_size : 0; r = amdgpu_dm_set_atomic_regamma(stream, regamma_lut, - regamma_size, has_rom); + regamma_size, has_rom, tf); if (r) return r; }