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[2620:137:e000::1:20]) by mx.google.com with ESMTP id r7-20020aa7d147000000b00522e4a1f1c2si1322473edo.469.2023.08.10.05.38.26; Thu, 10 Aug 2023 05:38:55 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=FPoCsWi9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235455AbjHJLyw (ORCPT + 99 others); Thu, 10 Aug 2023 07:54:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229848AbjHJLyt (ORCPT ); Thu, 10 Aug 2023 07:54:49 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B0F29136; Thu, 10 Aug 2023 04:54:48 -0700 (PDT) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37AAN4gX025158; Thu, 10 Aug 2023 11:54:40 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=+ucxebaIPcDw0GpcGhlF+1E0L7FzCTfQZFmRzOMrqfc=; b=FPoCsWi9RuUbwQn1czANW1queaDPjhomZbr/zlU+yTAlfBl2rz/0zO4RJzAW6S0UKae/ Ngc7OJDvInQDkCEB2df52b6MXSG6bY5ExY4KaIyY53RWYt3NCKop/Sk+mmTAUxKZnsFq ZaXz2g/knD5m+zMu2kdGuTfm3BAXPqznKMnWdtTMPty0zWu4+WhiBMczKBLDsvb5GIzJ VBou0y7qyOGoyrtPG4tzOn6Psp+cGj9AWF3I8HRTpUmA7YUl1EWGQdEWXnqsEd367MKE 7eboRAK9TT9MhDeMAZrccbx4/HbJ6yIAc+Fmp13qbSk3RuFye0c/Wv6zjlVo1Xad+IvN Yg== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3scw2urcg6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 10 Aug 2023 11:54:40 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 37ABsdV5018040 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 10 Aug 2023 11:54:39 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Thu, 10 Aug 2023 04:54:34 -0700 From: Luo Jie To: , , , , , , , , , , CC: , , , , , Luo Jie Subject: [PATCH v3 1/3] clk: qcom: branch: Add clk_branch2_mdio_ops Date: Thu, 10 Aug 2023 19:54:17 +0800 Message-ID: <20230810115419.25539-2-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230810115419.25539-1-quic_luoj@quicinc.com> References: <20230810115419.25539-1-quic_luoj@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ykHvaCsWsHRprMm_SNqZ-MGAQ2ynDGBL X-Proofpoint-ORIG-GUID: ykHvaCsWsHRprMm_SNqZ-MGAQ2ynDGBL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_10,2023-08-10_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 suspectscore=0 mlxlogscore=929 priorityscore=1501 adultscore=0 bulkscore=0 phishscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2308100100 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773845752355697926 X-GMAIL-MSGID: 1773845752355697926 Add the clk_branch2_mdio_ops for supporting clock controller where the hardware register is accessed by MDIO bus, and the spin clock can't be used because of sleep during the MDIO operation. The clock is enabled by the .prepare instead of .enable when the clk_branch2_mdio_ops is used. Signed-off-by: Luo Jie --- drivers/clk/qcom/clk-branch.c | 8 ++++++++ drivers/clk/qcom/clk-branch.h | 2 ++ 2 files changed, 10 insertions(+) diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c index fc4735f74f0f..95ed55c76b62 100644 --- a/drivers/clk/qcom/clk-branch.c +++ b/drivers/clk/qcom/clk-branch.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2013, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -153,3 +154,10 @@ const struct clk_ops clk_branch_simple_ops = { .is_enabled = clk_is_enabled_regmap, }; EXPORT_SYMBOL_GPL(clk_branch_simple_ops); + +const struct clk_ops clk_branch2_mdio_ops = { + .prepare = clk_branch2_enable, + .unprepare = clk_branch2_disable, + .is_prepared = clk_is_enabled_regmap, +}; +EXPORT_SYMBOL_GPL(clk_branch2_mdio_ops); diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h index 0cf800b9d08d..06e620968209 100644 --- a/drivers/clk/qcom/clk-branch.h +++ b/drivers/clk/qcom/clk-branch.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2013, The Linux Foundation. All rights reserved. */ +/* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef __QCOM_CLK_BRANCH_H__ #define __QCOM_CLK_BRANCH_H__ @@ -85,6 +86,7 @@ extern const struct clk_ops clk_branch_ops; extern const struct clk_ops clk_branch2_ops; extern const struct clk_ops clk_branch_simple_ops; extern const struct clk_ops clk_branch2_aon_ops; +extern const struct clk_ops clk_branch2_mdio_ops; #define to_clk_branch(_hw) \ container_of(to_clk_regmap(_hw), struct clk_branch, clkr)