From patchwork Tue Aug 8 20:18:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 132883 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c44e:0:b0:3f2:4152:657d with SMTP id w14csp2410045vqr; Tue, 8 Aug 2023 14:39:46 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFiJpSOL1JpL+I4CnveY0R05x08+I4sT/o0SvVtKO/+NlNEtyFVJFmzGgQBszOfRk0PwqOl X-Received: by 2002:a17:906:3299:b0:988:9b29:5653 with SMTP id 25-20020a170906329900b009889b295653mr611123ejw.77.1691530786076; Tue, 08 Aug 2023 14:39:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691530786; cv=none; d=google.com; s=arc-20160816; b=DS31mrvfn6klWEDuJiRC67a4nSWHNbt1Wo/OpzjqoCffSita9tsy3vS7VbhNl1ULfo 4qFLVdeKClmkir+j6Yl7DZpjdPbyZOMYybit4VYRyq21Q/4dCjFB7SacXeOvx9WxQglP 05oRGL5dqXzrAacyWLNbhY+L9t55bkpRU9uxCP4WcCvmVwkE+C6nx1fnePUb6K1fKnRM NUsuU/vdCuX3QCi/eBo99y/xo8TFm6oznE3TIUgOOz6wK4b90AI37Ec7jQ/T88eRucoo G3xfzupbuagexSALmzkEBSQ7LViPwei46szdQOPXSCSTnM05S1gz2NVnm6vg90uMExbR 929g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=DUKvmLPkldQCGnz+bLDL9y7pMNL4+AhpebRElbc5kvI=; fh=AOFcl182NPcBrF8V1t7LgZHFt53dFJmF6BGNBNOJCmM=; b=g+u1S+9pGy9v+qF1exBfbhti2zP26YV3CcGmrOivYlPcZ4fKMnK6TeV3zAPMmjFovG y6zm/kZrNTdnf+OCH61lF/CptbYXO8bhw/QNAxDOCmK4LGPrZIr0dYLKv+oB3Y5pbEKo kWw2OmT7Nx6levk6fv44/VlQY8coPILJcE2AdgUyxn+mEfeOfjCSgNbTHN5Vt7RzWTc5 71xa7QAH3X3D+BTHb0RvcUVF5XM/6bo67gDzBIsJmaqow3LiKunuxCr/ba3f6iqhUXOR jLXh7LvPtTgT/jHTDtJbMuKYTa6j2dfaLijldiNqvx4fdQm8FDomGtbE0xVD0aVHjMv5 Ygvg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=rxSodNIk; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id hk18-20020a170906c9d200b0099bd0b5a2b7si7812105ejb.542.2023.08.08.14.39.15; Tue, 08 Aug 2023 14:39:46 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=rxSodNIk; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234559AbjHHUoK (ORCPT + 99 others); Tue, 8 Aug 2023 16:44:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234531AbjHHUny (ORCPT ); Tue, 8 Aug 2023 16:43:54 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 223593C2D; Tue, 8 Aug 2023 13:18:59 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 378KIofP108265; Tue, 8 Aug 2023 15:18:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691525930; bh=DUKvmLPkldQCGnz+bLDL9y7pMNL4+AhpebRElbc5kvI=; h=From:To:Subject:Date:In-Reply-To:References; b=rxSodNIkY1e8Lm7NA3gipO+aHVD26uLzV76WcbqfnPtyBPRb7QX9CLPM0RQaJOVMq i7Vr9VeOa9LiiJtVkx11/LBaEH4rNDjRGbXOVrTHTXJsgFzY+oltm/rEqjsWtdwKjz gFynaE7Z73uNhSZIblteLKZVWKUOOMxMeyAfVg8E= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 378KIoAt033855 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Aug 2023 15:18:50 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 8 Aug 2023 15:18:49 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 8 Aug 2023 15:18:50 -0500 Received: from TI.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 378KIgrf028651; Tue, 8 Aug 2023 15:18:47 -0500 From: Apurva Nandan To: Apurva Nandan , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Udit Kumar , Hari Nagalla Subject: [PATCH v2 1/3] arm64: dts: ti: k3-j721s2-mcu: Add R5F cluster nodes Date: Wed, 9 Aug 2023 01:48:40 +0530 Message-ID: <20230808201842.292911-2-a-nandan@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808201842.292911-1-a-nandan@ti.com> References: <20230808201842.292911-1-a-nandan@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_PASS,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773698585300369302 X-GMAIL-MSGID: 1773698585300369302 From: Hari Nagalla The J721S2 SoCs have a dual-core Arm Cortex-R5F processor (R5FSS) subsystems/cluster in MCU voltage domain. It can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). The TCMs of both Cores are combined in LockStep-mode to provide a larger 128 KB of memory, but otherwise are functionally similar to those on J721E SoCs. Add the DT nodes for the MCU domain R5F cluster/subsystem, the two R5F cores are added as child nodes to each of the R5F cluster nodes. The clusters are configured to run in LockStep mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. The following firmware names are used by default for these cores, and can be overridden in a board dts file if desired: MCU R5FSS0 Core0: j721s2-mcu-r5f0_0-fw (both in LockStep and Split modes) MCU R5FSS0 Core1: j721s2-mcu-r5f0_1-fw (needed only in Split mode) Signed-off-by: Hari Nagalla Signed-off-by: Apurva Nandan --- .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 736ec5fa0ea2..d4624d8461b2 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -652,4 +652,44 @@ wkup_vtm0: temperature-sensor@42040000 { power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>; #thermal-sensor-cells = <1>; }; + + mcu_r5fss0: r5fss@41000000 { + compatible = "ti,j721s2-r5fss"; + ti,cluster-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x41000000 0x00 0x41000000 0x20000>, + <0x41400000 0x00 0x41400000 0x20000>; + power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; + + mcu_r5fss0_core0: r5f@41000000 { + compatible = "ti,j721s2-r5f"; + reg = <0x41000000 0x00010000>, + <0x41010000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <284>; + ti,sci-proc-ids = <0x01 0xff>; + resets = <&k3_reset 284 1>; + firmware-name = "j721s2-mcu-r5f0_0-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + + mcu_r5fss0_core1: r5f@41400000 { + compatible = "ti,j721s2-r5f"; + reg = <0x41400000 0x00010000>, + <0x41410000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&sms>; + ti,sci-dev-id = <285>; + ti,sci-proc-ids = <0x02 0xff>; + resets = <&k3_reset 285 1>; + firmware-name = "j721s2-mcu-r5f0_1-fw"; + ti,atcm-enable = <1>; + ti,btcm-enable = <1>; + ti,loczrama = <1>; + }; + }; };