Message ID | 20230807110733.77364-3-thippeswamy.havalige@amd.com |
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State | New |
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Mon, 7 Aug 2023 06:07:46 -0500 Received: from xhdthippesw40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Mon, 7 Aug 2023 06:07:43 -0500 From: Thippeswamy Havalige <thippeswamy.havalige@amd.com> To: <linux-kernel@vger.kernel.org>, <robh+dt@kernel.org>, <bhelgaas@google.com>, <krzysztof.kozlowski@linaro.org>, <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org> CC: <lpieralisi@kernel.org>, <bharat.kumar.gogada@amd.com>, <michal.simek@amd.com>, <linux-arm-kernel@lists.infradead.org>, "Thippeswamy Havalige" <thippeswamy.havalige@amd.com> Subject: [PATCH v1 2/2] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example. 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Series |
Fix ecam size value to discover 256 buses during
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Commit Message
Havalige, Thippeswamy
Aug. 7, 2023, 11:07 a.m. UTC
Update ECAM size in example to discover up to 256 buses. Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com> Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@amd.com> --- Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml index 8976025..426f90a 100644 --- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml @@ -118,7 +118,7 @@ examples: compatible = "xlnx,nwl-pcie-2.11"; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, - <0x80 0x00000000 0x0 0x1000000>; + <0x80 0x00000000 0x0 0x10000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>, <0x43000000 0x00000006 0x0 0x00000006 0x0 0x00000002 0x0>;