From patchwork Fri Aug 4 17:08:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 131302 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:c44e:0:b0:3f2:4152:657d with SMTP id w14csp38922vqr; Fri, 4 Aug 2023 11:59:08 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGEXxs9ntuE7a50KtIUxtOIOch56K0hRzIOWtsUDUGHzIb5KkhdR5u8y9WIYYkJ1Jj1s8Jg X-Received: by 2002:a17:907:a073:b0:988:8be0:3077 with SMTP id ia19-20020a170907a07300b009888be03077mr2183216ejc.31.1691175548271; Fri, 04 Aug 2023 11:59:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691175548; cv=none; d=google.com; s=arc-20160816; b=dOcc4t2TWPTKDJJCNhUWWCJ0yLCbg3kQeKV6XaiOK5IPS4RvenR7aMqnwsMjEZwWNn 5IUrveOcPq2GBcLDFkdTXlEGB6Mw5PqaVt0HlPA4gllFP/0DzU2ZVLYdEWLlPVUyJdbP uRkRb7m1SSQ1s9EKpUtQ1GbBCc82ITlEugZBG2edsiM4R5VuE6yK6rwBxvworlcbDFL9 mTs+xtf+z5PNgQ4JGawfEvjpMgCvMGNRNXRegkEF4JNpunYcGxjFDD78hpLNQrkCTq0Z OOme76QxSWmNuoZA5DZEyPRcUEP49w3tOuluZnYPU4kH4S4V66OCI9xFf20RxtQxRyQ4 Xuvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=Qv9xYCKglKwlbXzPz5PgR0Y3hcGtT3P8FsbyLNZZAOU=; fh=nThKA2TXpGJpfakb/DZinRN0V3NZQat6wKjbKP0xDlY=; b=L8hx+5MADGbBP8h4N7ky/X2rI6iax4K0wMe38He6o07MA9IFfx8sfBWOkMYXajnX8Y 7+8OJIZfLM8XI5v0SXfCDT9TjtqEP/dOBO5lwOKdjn/BDrTYGNDsQP8m+nYuECZOmHKS updDhTBqGS4093DOi6XfqNBmFLjR7CmeIn5rLtw3Z8BVa7MNIWTJIN8zgVZRZJQiGNyC dsK3hAO1rZmAxGxah4eNkHoPoNLeAVMb8CXGDHnLzs8cF/iHmkcaCEa7FwaZ0bBuL2fe no5HMr1qL5HCfQjPppjWmzFHLPdlOcuz0Hi1TcjLPcNKeBEE4FW/69ISwhYxQ/K1gNUs gbSg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id e10-20020a170906248a00b0099caf50c27fsi519997ejb.1046.2023.08.04.11.58.44; Fri, 04 Aug 2023 11:59:08 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232080AbjHDRJi (ORCPT + 99 others); Fri, 4 Aug 2023 13:09:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43914 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231954AbjHDRJY (ORCPT ); Fri, 4 Aug 2023 13:09:24 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id CEB924ECD; Fri, 4 Aug 2023 10:09:12 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0A37814BF; Fri, 4 Aug 2023 10:09:55 -0700 (PDT) Received: from donnerap.arm.com (donnerap.manchester.arm.com [10.32.100.58]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BC27E3F5A1; Fri, 4 Aug 2023 10:09:10 -0700 (PDT) From: Andre Przywara To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Icenowy Zheng , Piotr Oniszczuk , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/3] arm64: dts: allwinner: h616: Add OrangePi Zero 3 board support Date: Fri, 4 Aug 2023 18:08:56 +0100 Message-Id: <20230804170856.1237202-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230804170856.1237202-1-andre.przywara@arm.com> References: <20230804170856.1237202-1-andre.przywara@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773326091482986209 X-GMAIL-MSGID: 1773326091482986209 The OrangePi Zero 3 is a development board based on the Allwinner H618 SoC, which seems to be just an H616 with more L2 cache. The board itself is a slightly updated version of the Orange Pi Zero 2. It features: - Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU - 1/1.5/2/4 GiB LPDDR4 DRAM SKUs (only up to 1GB on the Zero2) - AXP313a PMIC (more capable AXP305 on the Zero2) - Raspberry-Pi-1 compatible GPIO header - extra 13 pin expansion header, exposing pins for 2x USB 2.0 ports - 1 USB 2.0 host port - 1 USB 2.0 type C port (power supply + OTG) - MicroSD slot - on-board 16MiB bootable SPI NOR flash (only 2MB on the Zero2) - 1Gbps Ethernet port (via Motorcomm YT8531 PHY) (RTL8211 on the Zero2) - micro-HDMI port - (yet) unsupported Allwinner WiFi/BT chip Add the devicetree file describing the currently supported features, namely LEDs, SD card, PMIC, SPI flash, USB. Ethernet seems unstable at the moment, though the basic functionality works. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../allwinner/sun50i-h618-orangepi-zero3.dts | 94 +++++++++++++++++++ 2 files changed, 95 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index 6a96494a2e0a3..3b0ad54062381 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -40,3 +40,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero3.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts new file mode 100644 index 0000000000000..96a6851728111 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2023 Arm Ltd. + */ + +/dts-v1/; + +#include "sun50i-h616-orangepi-zero.dtsi" + +/ { + model = "OrangePi Zero3"; + compatible = "xunlong,orangepi-zero3", "allwinner,sun50i-h618"; +}; + +&emac0 { + phy-supply = <®_dldo1>; +}; + +&ext_rgmii_phy { + motorcomm,clk-out-frequency-hz = <125000000>; +}; + +&mmc0 { + /* + * The schematic shows the card detect pin wired up to PF6, via an + * inverter, but it just doesn't work. + */ + broken-cd; + vmmc-supply = <®_dldo1>; +}; + +&r_i2c { + status = "okay"; + + axp313: pmic@36 { + compatible = "x-powers,axp313a"; + reg = <0x36>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&pio>; + interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>; /* PC9 */ + + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; + + regulators { + /* Supplies VCC-PLL, so needs to be always on. */ + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8"; + }; + + /* Supplies VCC-IO, so needs to be always on. */ + reg_dldo1: dldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3"; + }; + + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <990000>; + regulator-name = "vdd-gpu-sys"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-dram"; + }; + }; + }; +}; + +&pio { + vcc-pc-supply = <®_dldo1>; + vcc-pf-supply = <®_dldo1>; + vcc-pg-supply = <®_aldo1>; + vcc-ph-supply = <®_dldo1>; + vcc-pi-supply = <®_dldo1>; +};