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[2620:137:e000::1:20]) by mx.google.com with ESMTP id i4-20020a17090332c400b001bbb0fe3641si1503466plr.489.2023.08.04.02.03.14; Fri, 04 Aug 2023 02:03:29 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=bdVg24vJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234287AbjHDH3g (ORCPT + 99 others); Fri, 4 Aug 2023 03:29:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33702 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234161AbjHDH3G (ORCPT ); Fri, 4 Aug 2023 03:29:06 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3BE7D3AA6 for ; Fri, 4 Aug 2023 00:29:05 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 78E8066071B9; Fri, 4 Aug 2023 08:29:03 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1691134144; bh=JEghBTvHNSu8yfdUBd7VO3HyemOteRFeB2SfmGR0Hfs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bdVg24vJakDUuqCNbVft7PDFqonlDz85iOyEAaD02foARH5vQJ2GUAIM76VXt/8dR mcdv8isTfbpG9UDjqJ0vxWcj4GVIvcBYU5fN+eG5RKV/p9/uDYK0MWJ3lVdhnShunA 5A/2ORdPqozTDg4TKK7Elrp1UD7QKFuNrsENylQx5Ta6cqxAIecjNHHv7LETElQP9g GYWEfhBmeCDbhWpeLYEHq46OCrQ450s9oXLERe5uN8BFv9Kr4BBY9Cn/itglgn1Bt9 yLGnQnkL4Bt3qUyeacH8TeshWkoWEWnfUh+Xv+QeAArp33nGseYCifG+m+Thr8srSi x9U5PrvRuUmtw== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com Subject: [PATCH v10 08/16] drm/mediatek: De-commonize disp_aal/disp_gamma gamma_set functions Date: Fri, 4 Aug 2023 09:28:42 +0200 Message-ID: <20230804072850.89365-9-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> References: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773288617048389171 X-GMAIL-MSGID: 1773288617048389171 In preparation for adding a 12-bits gamma support for the DISP_GAMMA IP, remove the mtk_gamma_set_common() function and move the relevant bits in mtk_gamma_set() for DISP_GAMMA and mtk_aal_gamma_set() for DISP_AAL: since the latter has no more support for gamma manipulation (being moved to a different IP) in newer revisions, those functions are about to diverge and it makes no sense to keep a common one (with all the complications of passing common data and making exclusions for device driver data) for just a few bits. This commit brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_aal.c | 39 +++++++++++++++++++++-- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 1 - drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 34 ++++---------------- 3 files changed, 44 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/mediatek/mtk_disp_aal.c index bec035780db0..21b25470e9b7 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c @@ -17,10 +17,18 @@ #define DISP_AAL_EN 0x0000 #define AAL_EN BIT(0) +#define DISP_AAL_CFG 0x0020 +#define AAL_RELAY_MODE BIT(0) +#define AAL_GAMMA_LUT_EN BIT(1) #define DISP_AAL_SIZE 0x0030 #define DISP_AAL_SIZE_HSIZE GENMASK(28, 16) #define DISP_AAL_SIZE_VSIZE GENMASK(12, 0) #define DISP_AAL_OUTPUT_SIZE 0x04d8 +#define DISP_AAL_GAMMA_LUT 0x0700 +#define DISP_AAL_GAMMA_LUT_R GENMASK(29, 20) +#define DISP_AAL_GAMMA_LUT_G GENMASK(19, 10) +#define DISP_AAL_GAMMA_LUT_B GENMASK(9, 0) +#define DISP_AAL_LUT_BITS 10 #define DISP_AAL_LUT_SIZE 512 struct mtk_disp_aal_data { @@ -85,9 +93,36 @@ unsigned int mtk_aal_gamma_get_lut_size(struct device *dev) void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state) { struct mtk_disp_aal *aal = dev_get_drvdata(dev); + struct drm_color_lut *lut; + unsigned int i; + u32 cfg_val; + + /* If gamma is not supported in AAL, go out immediately */ + if (!(aal->data && aal->data->has_gamma)) + return; + + /* Also, if there's no gamma lut there's nothing to do here. */ + if (!state->gamma_lut) + return; + + cfg_val = readl(aal->regs + DISP_AAL_CFG); + lut = (struct drm_color_lut *)state->gamma_lut->data; + + for (i = 0; i < DISP_AAL_LUT_SIZE; i++) { + struct drm_color_lut hwlut = { + .red = drm_color_lut_extract(lut[i].red, DISP_AAL_LUT_BITS), + .green = drm_color_lut_extract(lut[i].green, DISP_AAL_LUT_BITS), + .blue = drm_color_lut_extract(lut[i].blue, DISP_AAL_LUT_BITS) + }; + u32 word; + + word = FIELD_PREP(DISP_AAL_GAMMA_LUT_R, hwlut.red); + word |= FIELD_PREP(DISP_AAL_GAMMA_LUT_G, hwlut.green); + word |= FIELD_PREP(DISP_AAL_GAMMA_LUT_B, hwlut.blue); + writel(word, (aal->regs + DISP_AAL_GAMMA_LUT) + (i * 4)); + } - if (aal->data && aal->data->has_gamma) - mtk_gamma_set_common(NULL, aal->regs, state); + writel(cfg_val, aal->regs + DISP_AAL_CFG); } void mtk_aal_start(struct device *dev) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index ca377265e5eb..54d3712e2afd 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -56,7 +56,6 @@ void mtk_gamma_config(struct device *dev, unsigned int w, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); unsigned int mtk_gamma_get_lut_size(struct device *dev); void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state); -void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crtc_state *state); void mtk_gamma_start(struct device *dev); void mtk_gamma_stop(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index ea91d3619716..001b98694761 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -73,42 +73,29 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev) return LUT_SIZE_DEFAULT; } -void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crtc_state *state) +void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) { - struct mtk_disp_gamma *gamma; + struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); unsigned int i; struct drm_color_lut *lut; void __iomem *lut_base; - bool lut_diff; - u16 lut_size; u32 cfg_val, word; /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) return; - /* If we're called from AAL, dev is NULL */ - gamma = dev ? dev_get_drvdata(dev) : NULL; - - if (gamma && gamma->data) { - lut_diff = gamma->data->lut_diff; - lut_size = gamma->data->lut_size; - } else { - lut_diff = false; - lut_size = LUT_SIZE_DEFAULT; - } - - cfg_val = readl(regs + DISP_GAMMA_CFG); - lut_base = regs + DISP_GAMMA_LUT; + cfg_val = readl(gamma->regs + DISP_GAMMA_CFG); + lut_base = gamma->regs + DISP_GAMMA_LUT; lut = (struct drm_color_lut *)state->gamma_lut->data; - for (i = 0; i < lut_size; i++) { + for (i = 0; i < gamma->data->lut_size; i++) { struct drm_color_lut diff, hwlut; hwlut.red = drm_color_lut_extract(lut[i].red, LUT_BITS_DEFAULT); hwlut.green = drm_color_lut_extract(lut[i].green, LUT_BITS_DEFAULT); hwlut.blue = drm_color_lut_extract(lut[i].blue, LUT_BITS_DEFAULT); - if (!lut_diff || (i % 2 == 0)) { + if (!gamma->data->lut_diff || (i % 2 == 0)) { word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); @@ -132,14 +119,7 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt /* Enable the gamma table */ cfg_val |= FIELD_PREP(GAMMA_LUT_EN, 1); - writel(cfg_val, regs + DISP_GAMMA_CFG); -} - -void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) -{ - struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); - - mtk_gamma_set_common(dev, gamma->regs, state); + writel(cfg_val, gamma->regs + DISP_GAMMA_CFG); } void mtk_gamma_config(struct device *dev, unsigned int w,