From patchwork Fri Aug 4 07:28:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 131016 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:44a:b0:3f2:4152:657d with SMTP id ez10csp117686vqb; Fri, 4 Aug 2023 01:45:50 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFuWQWZ0VDyn0KhY2XTC7+aNKtbd/JhJcVzHQJ1HgNfAMpgY10MUkAU6Q49V8xbUhSHqX/L X-Received: by 2002:a05:6a20:a124:b0:12e:caac:f263 with SMTP id q36-20020a056a20a12400b0012ecaacf263mr1563210pzk.20.1691138750439; Fri, 04 Aug 2023 01:45:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691138750; cv=none; d=google.com; s=arc-20160816; b=RIPOumCyrG4Wa0XYBmJMqQZRrWX0u+D/MmOkLkA6Br/WP2I16/S8WXPPWOPatpMy1k GFLIIp6+Sc/hMPgbDyaA2t0kCkLZNL1Yyx/M7lYcnucIlX/NLu+J9fwQId3nb4EyUeUJ RGv8T5ONX5CoiaxjdrabYeB9BgFW5LLb7Hhi+pxBf6wMFw/T1X0YXqiEUY1F1fvRBJDL egXHs36m80AYWoWhcwmtuZcSBnzIB0Zske/gnm8lytwH7THkjrPeWOsGepcR5J3nKfOS gkovmqtZfTSWJI0xI6ae2P/n1gk0rxSFv3DXPYq/Oo985ftTtT3g9/90+COPL7OAm/Yk nsIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=dm6Nc3M0XahRr5SgCwL2z7cNin/dAvbdfmHjVdvJV98=; fh=wVZEQimxp/UyE4Mf0Sn+nsZcfrBLHvkvU7kacOC/59o=; b=HK20Sccgh/OycgTRfGF2dtHlFYWXtg/5dmn+pJwHG76emtCWnANRXO7AB8EyBP6Cy2 fZPdQyUQdAsW4Z1ktfe5lCT00Cti2vD7qEp+prjgX4LTH3Bg0slJxYHd88k91qjT5/qL zx6UfNHzmXPNXCb3iC/18X+4Dfc+Sdj+ju/wZ2MpOiM68XNFkB0P67ibR3AwbQ7FbOBR G8rahn/zCUwfETx8bWbB0cZnZS4BdyMsfWcCUXLQwHsap6/kmv3PSqOAQbAf+wTzYyJY 2JqjmdyEgbeH1rjifOproAIask1uFI5+efgVhZmOFuSBqbGfQ2mWOxtOkgUqLPupCMyD lFsA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=VhvKyaSd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 10-20020a63020a000000b0053f327d0321si1482816pgc.323.2023.08.04.01.45.37; Fri, 04 Aug 2023 01:45:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=VhvKyaSd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234253AbjHDH30 (ORCPT + 99 others); Fri, 4 Aug 2023 03:29:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233979AbjHDH3E (ORCPT ); Fri, 4 Aug 2023 03:29:04 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C4BA23ABB for ; Fri, 4 Aug 2023 00:29:02 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id E5A2366071BF; Fri, 4 Aug 2023 08:29:00 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1691134141; bh=jQ1ukxJYhgqz3VRiaaOzbMrQXLA2ENp1Hjs7vpajFxc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VhvKyaSdv9t8JEDwXh9pWZPN31nlksxKdJmcOxMZ1J+QKFpWSwChOcQprSZ6E1SRq dBnPksX9NkbHAUM51iyeZhn4XWQAPhFnKsGQnJq361xj8AT1yvRJQeZ/veh+WCjxUP +IHVSRIjLXD+Nc2TUnBdD6Q8D5jPEItICRKrz0ol9SolAhd5Im8LyR4hXtGjJ6mRTn 5YMHfg1qytYrgz2dsnn2SL2UYK0rhmKbZ1DH/NIoNiS8frYlgqIb9ksEbZ6hhcCQ6x HA09kLwOZPUuD4FSvif/yodCNf8nqMOE0IYr+gfkDY7esu0JqdfelW/6hUIpbxj82H lXQuTOBbrkCzg== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, "Jason-JH . Lin" , Alexandre Mergnat Subject: [PATCH v10 05/16] drm/mediatek: gamma: Enable the Gamma LUT table only after programming Date: Fri, 4 Aug 2023 09:28:39 +0200 Message-ID: <20230804072850.89365-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> References: <20230804072850.89365-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773287506009106186 X-GMAIL-MSGID: 1773287506009106186 Move the write to DISP_GAMMA_CFG to enable the Gamma LUT to after programming the actual table to avoid potential visual glitches during table modification. Note: GAMMA should get enabled in between vblanks, but this requires many efforts in order to make this happen, as that requires migrating all of the writes to make use of CMDQ instead of cpu writes and that's not trivial. For this reason, this patch only moves the LUT enable. The CMDQ rework will come at a later time. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index fd6a75a64a9f..18b102bef370 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -68,12 +68,12 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev) void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crtc_state *state) { struct mtk_disp_gamma *gamma; - unsigned int i, reg; + unsigned int i; struct drm_color_lut *lut; void __iomem *lut_base; bool lut_diff; u16 lut_size; - u32 word; + u32 cfg_val, word; /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) @@ -90,9 +90,7 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt lut_size = LUT_SIZE_DEFAULT; } - reg = readl(regs + DISP_GAMMA_CFG); - reg = reg | GAMMA_LUT_EN; - writel(reg, regs + DISP_GAMMA_CFG); + cfg_val = readl(regs + DISP_GAMMA_CFG); lut_base = regs + DISP_GAMMA_LUT; lut = (struct drm_color_lut *)state->gamma_lut->data; for (i = 0; i < lut_size; i++) { @@ -122,6 +120,11 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt } writel(word, (lut_base + i * 4)); } + + /* Enable the gamma table */ + cfg_val = cfg_val | GAMMA_LUT_EN; + + writel(cfg_val, regs + DISP_GAMMA_CFG); } void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state)