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Thu, 3 Aug 2023 18:01:44 -0500 From: Smita Koralahalli To: , , CC: Bjorn Helgaas , , Lukas Wunner , Kuppuswamy Sathyanarayanan , Mahesh J Salgaonkar , Alison Schofield , "Vishal Verma" , Ira Weiny , "Ben Widawsky" , Dan Williams , Jonathan Cameron , Yazen Ghannam , Terry Bowman , Robert Richter , Smita Koralahalli Subject: [PATCH v3 3/3] cxl/pci: Replace host_bridge->native_aer with pcie_aer_is_native() Date: Thu, 3 Aug 2023 23:01:29 +0000 Message-ID: <20230803230129.127590-4-Smita.KoralahalliChannabasappa@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230803230129.127590-1-Smita.KoralahalliChannabasappa@amd.com> References: <20230803230129.127590-1-Smita.KoralahalliChannabasappa@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989EC:EE_|BL0PR12MB4963:EE_ X-MS-Office365-Filtering-Correlation-Id: d4381ef0-5a58-4f72-81ce-08db94759cca X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Smita Koralahalli Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Robert Richter --- v2: Replaced pcie_aer_is_native() at a later stage for automated backports. v3: Added more context to commit message. Added "Reviewed-by" tag. --- drivers/cxl/pci.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 2323169b6e5f..44a21ab7add5 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -529,7 +529,6 @@ static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, static int cxl_pci_ras_unmask(struct pci_dev *pdev) { - struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus); struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); void __iomem *addr; u32 orig_val, val, mask; @@ -542,7 +541,7 @@ static int cxl_pci_ras_unmask(struct pci_dev *pdev) } /* BIOS has PCIe AER error control */ - if (!host_bridge->native_aer) + if (!pcie_aer_is_native(pdev)) return 0; rc = pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap);