Message ID | 20230802205309.257392-11-afd@ti.com |
---|---|
State | New |
Headers |
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[2620:137:e000::1:20]) by mx.google.com with ESMTP id kz7-20020a170902f9c700b001bb0fc56a1esi11254915plb.197.2023.08.02.14.35.42; Wed, 02 Aug 2023 14:35:56 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=N+WpwMIx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232831AbjHBUxh (ORCPT <rfc822;maxi.paulin@gmail.com> + 99 others); Wed, 2 Aug 2023 16:53:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229801AbjHBUxY (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Wed, 2 Aug 2023 16:53:24 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D473C26B5; Wed, 2 Aug 2023 13:53:22 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 372KrH1G109460; Wed, 2 Aug 2023 15:53:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1691009597; bh=t0NFPm/eBGsI8PsBULav5hRKKRo235LNB1aMsQWzZIc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=N+WpwMIxhKB8CkjOZxM6bMRs6mi5EvcCgW2R6RAhqjBpEapMVGyIxxPDnElyio5Va pMBNtgYR9RkqSF1ehxFpLa9rJYNHhHkniiJ0hBdSXxRfFcEE1euaM49ko7juF8cslt lq0SmNFS4sey9bhbJEqPLFuS5wdMHN49w8aljtYQ= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 372KrHxJ018948 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 2 Aug 2023 15:53:17 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 2 Aug 2023 15:53:17 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 2 Aug 2023 15:53:16 -0500 Received: from lelv0326.itg.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 372KrASH090834; Wed, 2 Aug 2023 15:53:16 -0500 From: Andrew Davis <afd@ti.com> To: Nishanth Menon <nm@ti.com>, Vignesh Raghavendra <vigneshr@ti.com>, Tero Kristo <kristo@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, <linux-arm-kernel@lists.infradead.org> CC: <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, Andrew Davis <afd@ti.com> Subject: [PATCH 10/13] arm64: dts: ti: k3-j7200: Enable GPIO nodes at the board level Date: Wed, 2 Aug 2023 15:53:06 -0500 Message-ID: <20230802205309.257392-11-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230802205309.257392-1-afd@ti.com> References: <20230802205309.257392-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773154763276916415 X-GMAIL-MSGID: 1773154763276916415 |
Series |
Another round of K3 DTSI disables
|
|
Commit Message
Andrew Davis
Aug. 2, 2023, 8:53 p.m. UTC
GPIO nodes defined in the top-level J7200 SoC dtsi files are incomplete
and may not be functional unless they are extended with pinmux and
device information.
Disable the GPIO nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
---
.../boot/dts/ti/k3-j7200-common-proc-board.dts | 18 ++++--------------
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 4 ++++
.../arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 2 ++
3 files changed, 10 insertions(+), 14 deletions(-)
Comments
Andrew, On 03/08/23 02:23, Andrew Davis wrote: > GPIO nodes defined in the top-level J7200 SoC dtsi files are incomplete > and may not be functional unless they are extended with pinmux and > device information. > > Disable the GPIO nodes in the dtsi files and only enable the ones that > are actually pinned out on a given board. > > Signed-off-by: Andrew Davis <afd@ti.com> > --- > .../boot/dts/ti/k3-j7200-common-proc-board.dts | 18 ++++-------------- > arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 4 ++++ > .../arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 2 ++ > 3 files changed, 10 insertions(+), 14 deletions(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts > index dee9056f56051..4a5c4f36baeec 100644 > --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts > +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts > @@ -240,27 +240,17 @@ &main_uart3 { > pinctrl-0 = <&main_uart3_pins_default>; > }; > > -&main_gpio2 { > - status = "disabled"; > -}; > - > -&main_gpio4 { > - status = "disabled"; > -}; > - > -&main_gpio6 { > - status = "disabled"; > +&main_gpio0 { > + status = "okay"; > + /* default pins */ Small question, where is the pmx for main_gpio0? What does "default pins" refer to here? Where are they pinmuxed? > }; > > &wkup_gpio0 { > + status = "okay"; > pinctrl-names = "default"; > pinctrl-0 = <&wkup_gpio_pins_default>; > }; > > -&wkup_gpio1 { > - status = "disabled"; > -}; > - > &mcu_cpsw { > pinctrl-names = "default"; > pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; > diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi > index 5d7542ba41b93..6a776f3bbcb19 100644 > --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi > @@ -832,6 +832,7 @@ main_gpio0: gpio@600000 { > power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; > clocks = <&k3_clks 105 0>; > clock-names = "gpio"; > + status = "disabled"; > }; > > main_gpio2: gpio@610000 { > @@ -849,6 +850,7 @@ main_gpio2: gpio@610000 { > power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; > clocks = <&k3_clks 107 0>; > clock-names = "gpio"; > + status = "disabled"; > }; > > main_gpio4: gpio@620000 { > @@ -866,6 +868,7 @@ main_gpio4: gpio@620000 { > power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; > clocks = <&k3_clks 109 0>; > clock-names = "gpio"; > + status = "disabled"; > }; > > main_gpio6: gpio@630000 { > @@ -883,6 +886,7 @@ main_gpio6: gpio@630000 { > power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; > clocks = <&k3_clks 111 0>; > clock-names = "gpio"; > + status = "disabled"; > }; > > main_spi0: spi@2100000 { > diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi > index 571eb0e2eac92..5ae7320efad7b 100644 > --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi > @@ -297,6 +297,7 @@ wkup_gpio0: gpio@42110000 { > power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; > clocks = <&k3_clks 113 0>; > clock-names = "gpio"; > + status = "disabled"; > }; > > wkup_gpio1: gpio@42100000 { > @@ -313,6 +314,7 @@ wkup_gpio1: gpio@42100000 { > power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; > clocks = <&k3_clks 114 0>; > clock-names = "gpio"; > + status = "disabled"; > }; > > mcu_navss: bus@28380000 {
On 8/7/23 12:38 AM, Dhruva Gole wrote: > Andrew, > > On 03/08/23 02:23, Andrew Davis wrote: >> GPIO nodes defined in the top-level J7200 SoC dtsi files are incomplete >> and may not be functional unless they are extended with pinmux and >> device information. >> >> Disable the GPIO nodes in the dtsi files and only enable the ones that >> are actually pinned out on a given board. >> >> Signed-off-by: Andrew Davis <afd@ti.com> >> --- >> .../boot/dts/ti/k3-j7200-common-proc-board.dts | 18 ++++-------------- >> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 4 ++++ >> .../arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 2 ++ >> 3 files changed, 10 insertions(+), 14 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts >> index dee9056f56051..4a5c4f36baeec 100644 >> --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts >> +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts >> @@ -240,27 +240,17 @@ &main_uart3 { >> pinctrl-0 = <&main_uart3_pins_default>; >> }; >> -&main_gpio2 { >> - status = "disabled"; >> -}; >> - >> -&main_gpio4 { >> - status = "disabled"; >> -}; >> - >> -&main_gpio6 { >> - status = "disabled"; >> +&main_gpio0 { >> + status = "okay"; >> + /* default pins */ > > Small question, where is the pmx for main_gpio0? What does "default pins" > refer to here? Where are they pinmuxed? > Good question, where is the pmx for main_gpio0? I don't know, it was never defined before either, we only are noticing this now as we are disabling by default instead of leaving an unfinished node enabled by default. (another benefit of this disabled by default scheme). What is really happening is GPIO nodes we tend to pinmux differently than normal device nodes. Their pinmux selections tends to be spread out in all the nodes that make use of these GPIO pins, not all together here in this node. For instance in this device we use one of the main_gpio0 pins as a GPIO toggled regulator, and we define the pinmux for it in that node (see vdd-sd-dv-default-pins). We can either define the rest of the pins not used elsewhere here, or we can consider GPIO an exception to the rule, I'd say the latter is fine for now. Andrew >> }; >> &wkup_gpio0 { >> + status = "okay"; >> pinctrl-names = "default"; >> pinctrl-0 = <&wkup_gpio_pins_default>; >> }; >> -&wkup_gpio1 { >> - status = "disabled"; >> -}; >> - >> &mcu_cpsw { >> pinctrl-names = "default"; >> pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; >> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi >> index 5d7542ba41b93..6a776f3bbcb19 100644 >> --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi >> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi >> @@ -832,6 +832,7 @@ main_gpio0: gpio@600000 { >> power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; >> clocks = <&k3_clks 105 0>; >> clock-names = "gpio"; >> + status = "disabled"; >> }; >> main_gpio2: gpio@610000 { >> @@ -849,6 +850,7 @@ main_gpio2: gpio@610000 { >> power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; >> clocks = <&k3_clks 107 0>; >> clock-names = "gpio"; >> + status = "disabled"; >> }; >> main_gpio4: gpio@620000 { >> @@ -866,6 +868,7 @@ main_gpio4: gpio@620000 { >> power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; >> clocks = <&k3_clks 109 0>; >> clock-names = "gpio"; >> + status = "disabled"; >> }; >> main_gpio6: gpio@630000 { >> @@ -883,6 +886,7 @@ main_gpio6: gpio@630000 { >> power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; >> clocks = <&k3_clks 111 0>; >> clock-names = "gpio"; >> + status = "disabled"; >> }; >> main_spi0: spi@2100000 { >> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi >> index 571eb0e2eac92..5ae7320efad7b 100644 >> --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi >> +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi >> @@ -297,6 +297,7 @@ wkup_gpio0: gpio@42110000 { >> power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; >> clocks = <&k3_clks 113 0>; >> clock-names = "gpio"; >> + status = "disabled"; >> }; >> wkup_gpio1: gpio@42100000 { >> @@ -313,6 +314,7 @@ wkup_gpio1: gpio@42100000 { >> power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; >> clocks = <&k3_clks 114 0>; >> clock-names = "gpio"; >> + status = "disabled"; >> }; >> mcu_navss: bus@28380000 { >
On 10:28-20230807, Andrew Davis wrote: > On 8/7/23 12:38 AM, Dhruva Gole wrote: > > Andrew, > > > > On 03/08/23 02:23, Andrew Davis wrote: > > > GPIO nodes defined in the top-level J7200 SoC dtsi files are incomplete > > > and may not be functional unless they are extended with pinmux and > > > device information. > > > > > > Disable the GPIO nodes in the dtsi files and only enable the ones that > > > are actually pinned out on a given board. > > > > > > Signed-off-by: Andrew Davis <afd@ti.com> > > > --- > > > .../boot/dts/ti/k3-j7200-common-proc-board.dts | 18 ++++-------------- > > > arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 4 ++++ > > > .../arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 2 ++ > > > 3 files changed, 10 insertions(+), 14 deletions(-) > > > > > > diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts > > > index dee9056f56051..4a5c4f36baeec 100644 > > > --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts > > > +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts > > > @@ -240,27 +240,17 @@ &main_uart3 { > > > pinctrl-0 = <&main_uart3_pins_default>; > > > }; > > > -&main_gpio2 { > > > - status = "disabled"; > > > -}; > > > - > > > -&main_gpio4 { > > > - status = "disabled"; > > > -}; > > > - > > > -&main_gpio6 { > > > - status = "disabled"; > > > +&main_gpio0 { > > > + status = "okay"; > > > + /* default pins */ > > > > Small question, where is the pmx for main_gpio0? What does "default pins" > > refer to here? Where are they pinmuxed? > > > > Good question, where is the pmx for main_gpio0? I don't know, it was > never defined before either, we only are noticing this now as we are > disabling by default instead of leaving an unfinished node enabled > by default. (another benefit of this disabled by default scheme). > > What is really happening is GPIO nodes we tend to pinmux differently > than normal device nodes. Their pinmux selections tends to be spread > out in all the nodes that make use of these GPIO pins, not all together > here in this node. > > For instance in this device we use one of the main_gpio0 pins as a > GPIO toggled regulator, and we define the pinmux for it in that node > (see vdd-sd-dv-default-pins). > > We can either define the rest of the pins not used elsewhere > here, or we can consider GPIO an exception to the rule, I'd say > the latter is fine for now. GPIO pinmux are typically defined where they need - the only place where they are explicitly called out in gpio is when they are meant to be used by libgpio - typically in the case of dev boards. Just drop the comments of /* default pins */ - that is just mis-leading.
On 8/7/23 10:42 AM, Nishanth Menon wrote: > On 10:28-20230807, Andrew Davis wrote: >> On 8/7/23 12:38 AM, Dhruva Gole wrote: >>> Andrew, >>> >>> On 03/08/23 02:23, Andrew Davis wrote: >>>> GPIO nodes defined in the top-level J7200 SoC dtsi files are incomplete >>>> and may not be functional unless they are extended with pinmux and >>>> device information. >>>> >>>> Disable the GPIO nodes in the dtsi files and only enable the ones that >>>> are actually pinned out on a given board. >>>> >>>> Signed-off-by: Andrew Davis <afd@ti.com> >>>> --- >>>> .../boot/dts/ti/k3-j7200-common-proc-board.dts | 18 ++++-------------- >>>> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 4 ++++ >>>> .../arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 2 ++ >>>> 3 files changed, 10 insertions(+), 14 deletions(-) >>>> >>>> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts >>>> index dee9056f56051..4a5c4f36baeec 100644 >>>> --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts >>>> +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts >>>> @@ -240,27 +240,17 @@ &main_uart3 { >>>> pinctrl-0 = <&main_uart3_pins_default>; >>>> }; >>>> -&main_gpio2 { >>>> - status = "disabled"; >>>> -}; >>>> - >>>> -&main_gpio4 { >>>> - status = "disabled"; >>>> -}; >>>> - >>>> -&main_gpio6 { >>>> - status = "disabled"; >>>> +&main_gpio0 { >>>> + status = "okay"; >>>> + /* default pins */ >>> >>> Small question, where is the pmx for main_gpio0? What does "default pins" >>> refer to here? Where are they pinmuxed? >>> >> >> Good question, where is the pmx for main_gpio0? I don't know, it was >> never defined before either, we only are noticing this now as we are >> disabling by default instead of leaving an unfinished node enabled >> by default. (another benefit of this disabled by default scheme). >> >> What is really happening is GPIO nodes we tend to pinmux differently >> than normal device nodes. Their pinmux selections tends to be spread >> out in all the nodes that make use of these GPIO pins, not all together >> here in this node. >> >> For instance in this device we use one of the main_gpio0 pins as a >> GPIO toggled regulator, and we define the pinmux for it in that node >> (see vdd-sd-dv-default-pins). >> >> We can either define the rest of the pins not used elsewhere >> here, or we can consider GPIO an exception to the rule, I'd say >> the latter is fine for now. > > > GPIO pinmux are typically defined where they need - the only place where > they are explicitly called out in gpio is when they are meant to be used by > libgpio - typically in the case of dev boards. > > Just drop the comments of /* default pins */ - that is just mis-leading. > True, will drop the comment for v2. Andrew
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index dee9056f56051..4a5c4f36baeec 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -240,27 +240,17 @@ &main_uart3 { pinctrl-0 = <&main_uart3_pins_default>; }; -&main_gpio2 { - status = "disabled"; -}; - -&main_gpio4 { - status = "disabled"; -}; - -&main_gpio6 { - status = "disabled"; +&main_gpio0 { + status = "okay"; + /* default pins */ }; &wkup_gpio0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&wkup_gpio_pins_default>; }; -&wkup_gpio1 { - status = "disabled"; -}; - &mcu_cpsw { pinctrl-names = "default"; pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 5d7542ba41b93..6a776f3bbcb19 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -832,6 +832,7 @@ main_gpio0: gpio@600000 { power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 105 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio2: gpio@610000 { @@ -849,6 +850,7 @@ main_gpio2: gpio@610000 { power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 107 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio4: gpio@620000 { @@ -866,6 +868,7 @@ main_gpio4: gpio@620000 { power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 109 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio6: gpio@630000 { @@ -883,6 +886,7 @@ main_gpio6: gpio@630000 { power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 111 0>; clock-names = "gpio"; + status = "disabled"; }; main_spi0: spi@2100000 { diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 571eb0e2eac92..5ae7320efad7b 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -297,6 +297,7 @@ wkup_gpio0: gpio@42110000 { power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 113 0>; clock-names = "gpio"; + status = "disabled"; }; wkup_gpio1: gpio@42100000 { @@ -313,6 +314,7 @@ wkup_gpio1: gpio@42100000 { power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 114 0>; clock-names = "gpio"; + status = "disabled"; }; mcu_navss: bus@28380000 {