From patchwork Wed Aug 2 17:09:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Easwar Hariharan X-Patchwork-Id: 130026 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9f41:0:b0:3e4:2afc:c1 with SMTP id v1csp627181vqx; Wed, 2 Aug 2023 10:54:05 -0700 (PDT) X-Google-Smtp-Source: APBJJlHrJU1+4yOEIbrCsTXPhS6vJsbP0BnPwqAypebiOVMAChJQAxgG/GYKfUvuY7Ar54C8xsEm X-Received: by 2002:a17:902:9b94:b0:1bb:a6db:3fd0 with SMTP id y20-20020a1709029b9400b001bba6db3fd0mr14226304plp.69.1690998845509; Wed, 02 Aug 2023 10:54:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690998845; cv=none; d=google.com; s=arc-20160816; b=xn4Csj14Y5zbeB4T7C/vViyq3qBnH8pzo1ITGf4iCzNdzZ/EwZjOMVvN2JJlRFj2IE Cj8c+bx6fiFBi2RzowYnTbH/q+dxHQd8JRt9/a2sOyFqziRVx5MN7hcEA5UGD0D56u9Y tugKf/EnveF/nGAqyJ66BAaqWSzkFpWNEOcS/aZ+6hiZtBW+cMpmxDxa6bx3VxPHSNBF AalO2VcbsGzcpzRwzJsLqtkUz9FvGdXatkFWk73sUVfz9Tj1AbJ963NVxgIoy8E+24ba QzJNO+Nd4A+cL9g+47TXEs0gvYtQOYfh/qIGpLQcPK7UMpRFXAMtWUMTRBRSYTBoIkiR Z2PA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:dkim-filter; bh=fDMlaBv0OrmjGT2rCt6r3VpG49OJGOp86FWwQR6AG8I=; fh=yG7386C55dhLYxQOqLFF0MJf6TIRCYeKmFoR6/rUG7c=; b=szmLOHwQNi5TXnw3brjMVTT6cv8fCMIDS0wyS/e0HI2hUVyhg6eVQzUuxYbGcws9X1 Rfpwr86vw3b+YcrclZN2+TxKq9nQe5e7OZG6JAiFBKEy4JwHxuzxppZd1Es5cTTMmliz RFyBsHly2CMKXpaFc6lHY3BDldipLT+tYhh3nmmjjppz0VxNQe68b90b8IA0yXL7Mxnx 7sMaS2+pF2EqeyaBrXxLLqYvrTIldKWeikLLcG1qxL+4oxbDw7V3JFBxqGT7bunAudN4 Yw0JJIfGKdlYGm+w9w+J0ZHAwBi/Lth2nqwBLkMrOsaHFTixmE45XyHsBafzBCUvD4Hd xd5A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linux.microsoft.com header.s=default header.b=MBrgUE5y; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linux.microsoft.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id jc9-20020a17090325c900b001b8bab3d5dasi10436114plb.108.2023.08.02.10.53.51; Wed, 02 Aug 2023 10:54:05 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linux.microsoft.com header.s=default header.b=MBrgUE5y; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linux.microsoft.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230209AbjHBRJ0 (ORCPT + 99 others); Wed, 2 Aug 2023 13:09:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34510 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229541AbjHBRJW (ORCPT ); Wed, 2 Aug 2023 13:09:22 -0400 Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id E5FD01723; Wed, 2 Aug 2023 10:09:20 -0700 (PDT) Received: from rrs24-12-35.corp.microsoft.com (unknown [131.107.147.181]) by linux.microsoft.com (Postfix) with ESMTPSA id 5545A238C44A; Wed, 2 Aug 2023 10:09:20 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 5545A238C44A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1690996160; bh=fDMlaBv0OrmjGT2rCt6r3VpG49OJGOp86FWwQR6AG8I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MBrgUE5yyF4lmQsGR5fA3xCwtE6REdRcq3HEpVDdlPJU1X3nSlJC4O3K93CWGLCVS +fIRyAe9Xt/odCqQ6+lRf/gJgmIzf/5vjCa9EIEiiS1dlF7aESNG02wqsq+BMIBSnN eg+dumcBJvFcSR4Ejt30AUd0M+B8rAjPTOdjyEcw= From: Easwar Hariharan To: stable@vger.kernel.org Cc: easwar.hariharan@microsoft.com, Robin Murphy , Nicolin Chen , Will Deacon , Catalin Marinas , Jonathan Corbet , Joerg Roedel , Sasha Levin , Yicong Yang , Tomas Krcka , linux-arm-kernel@lists.infradead.org (moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)), linux-doc@vger.kernel.org (open list:DOCUMENTATION), linux-kernel@vger.kernel.org (open list), iommu@lists.linux-foundation.org (open list:IOMMU DRIVERS), iommu@lists.linux.dev (open list:IOMMU DRIVERS) Subject: [PATCH v2 6.1 1/4] iommu/arm-smmu-v3: Work around MMU-600 erratum 1076982 Date: Wed, 2 Aug 2023 17:09:08 +0000 Message-Id: <20230802170911.1593275-2-eahariha@linux.microsoft.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230802170911.1593275-1-eahariha@linux.microsoft.com> References: <20230802170911.1593275-1-eahariha@linux.microsoft.com> MIME-Version: 1.0 X-Spam-Status: No, score=-19.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,ENV_AND_HDR_SPF_MATCH,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE,USER_IN_DEF_DKIM_WL, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773140805476166162 X-GMAIL-MSGID: 1773140805476166162 From: Robin Murphy commit f322e8af35c7f23a8c08b595c38d6c855b2d836f upstream MMU-600 versions prior to r1p0 fail to correctly generate a WFE wakeup event when the command queue transitions fom full to non-full. We can easily work around this by simply hiding the SEV capability such that we fall back to polling for space in the queue - since MMU-600 implements MSIs we wouldn't expect to need SEV for sync completion either, so this should have little to no impact. Signed-off-by: Robin Murphy Reviewed-by: Nicolin Chen Tested-by: Nicolin Chen Link: https://lore.kernel.org/r/08adbe3d01024d8382a478325f73b56851f76e49.1683731256.git.robin.murphy@arm.com Signed-off-by: Will Deacon Signed-off-by: Easwar Hariharan --- Documentation/arm64/silicon-errata.rst | 2 ++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 29 +++++++++++++++++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 6 +++++ 3 files changed, 37 insertions(+) diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst index f64354f8a79f..55e1e074dec1 100644 --- a/Documentation/arm64/silicon-errata.rst +++ b/Documentation/arm64/silicon-errata.rst @@ -122,6 +122,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | MMU-500 | #841119,826419 | N/A | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | MMU-600 | #1076982 | N/A | ++----------------+-----------------+-----------------+-----------------------------+ +----------------+-----------------+-----------------+-----------------------------+ | Broadcom | Brahma-B53 | N/A | ARM64_ERRATUM_845719 | +----------------+-----------------+-----------------+-----------------------------+ diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index bcdb2cbdda97..782d040a829c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3459,6 +3459,33 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool bypass) return 0; } +#define IIDR_IMPLEMENTER_ARM 0x43b +#define IIDR_PRODUCTID_ARM_MMU_600 0x483 + +static void arm_smmu_device_iidr_probe(struct arm_smmu_device *smmu) +{ + u32 reg; + unsigned int implementer, productid, variant, revision; + + reg = readl_relaxed(smmu->base + ARM_SMMU_IIDR); + implementer = FIELD_GET(IIDR_IMPLEMENTER, reg); + productid = FIELD_GET(IIDR_PRODUCTID, reg); + variant = FIELD_GET(IIDR_VARIANT, reg); + revision = FIELD_GET(IIDR_REVISION, reg); + + switch (implementer) { + case IIDR_IMPLEMENTER_ARM: + switch (productid) { + case IIDR_PRODUCTID_ARM_MMU_600: + /* Arm erratum 1076982 */ + if (variant == 0 && revision <= 2) + smmu->features &= ~ARM_SMMU_FEAT_SEV; + break; + } + break; + } +} + static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) { u32 reg; @@ -3664,6 +3691,8 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) smmu->ias = max(smmu->ias, smmu->oas); + arm_smmu_device_iidr_probe(smmu); + if (arm_smmu_sva_supported(smmu)) smmu->features |= ARM_SMMU_FEAT_SVA; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 4cb136f07914..5964e02c4e57 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -69,6 +69,12 @@ #define IDR5_VAX GENMASK(11, 10) #define IDR5_VAX_52_BIT 1 +#define ARM_SMMU_IIDR 0x18 +#define IIDR_PRODUCTID GENMASK(31, 20) +#define IIDR_VARIANT GENMASK(19, 16) +#define IIDR_REVISION GENMASK(15, 12) +#define IIDR_IMPLEMENTER GENMASK(11, 0) + #define ARM_SMMU_CR0 0x20 #define CR0_ATSCHK (1 << 4) #define CR0_CMDQEN (1 << 3)