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[v7,15/15] MAINTAINERS: Add entry for RISC-V AIA drivers

Message ID	20230802150018.327079-16-apatel@ventanamicro.com
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; From: Anup Patel <apatel@ventanamicro.com> To: Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Frank Rowand <frowand.list@gmail.com>, Conor Dooley <conor+dt@kernel.org> Cc: Atish Patra <atishp@atishpatra.org>, Andrew Jones <ajones@ventanamicro.com>, Sunil V L <sunilvl@ventanamicro.com>, Saravana Kannan <saravanak@google.com>, Anup Patel <anup@brainfault.org>, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel <apatel@ventanamicro.com> Subject: [PATCH v7 15/15] MAINTAINERS: Add entry for RISC-V AIA drivers Date: Wed, 2 Aug 2023 20:30:18 +0530 Message-Id: <20230802150018.327079-16-apatel@ventanamicro.com> In-Reply-To: <20230802150018.327079-1-apatel@ventanamicro.com> References: <20230802150018.327079-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	Linux RISC-V AIA Support \| [v7,00/15] Linux RISC-V AIA Support [v7,01/15] RISC-V: Add riscv_get_intc_hartid() function [v7,02/15] of: property: Add fw_devlink support for msi-parent [v7,03/15] drivers: irqchip/riscv-intc: Mark all INTC nodes as initialized [v7,04/15] irqchip/sifive-plic: Fix syscore registration for multi-socket systems [v7,05/15] irqchip/sifive-plic: Convert PLIC driver into a platform driver [v7,06/15] irqchip/riscv-intc: Add support for RISC-V AIA [v7,07/15] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller [v7,08/15] irqchip: Add RISC-V incoming MSI controller early driver [v7,09/15] irqchip/riscv-imsic: Add support for platform MSI irqdomain [v7,10/15] irqchip/riscv-imsic: Add support for PCI MSI irqdomain [v7,11/15] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC [v7,12/15] irqchip: Add RISC-V advanced PLIC driver for direct-mode [v7,13/15] irqchip/riscv-aplic: Add support for MSI-mode [v7,14/15] RISC-V: Select APLIC and IMSIC drivers [v7,15/15] MAINTAINERS: Add entry for RISC-V AIA drivers

Commit Message

Anup Patel Aug. 2, 2023, 3 p.m. UTC

  Add myself as maintainer for RISC-V AIA drivers including the
RISC-V INTC driver which supports both AIA and non-AIA platforms.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 MAINTAINERS | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff mbox series

Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index 53b7ca804465..8e315aaa20bc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -18259,6 +18259,20 @@  S:	Maintained
 F:	drivers/mtd/nand/raw/r852.c
 F:	drivers/mtd/nand/raw/r852.h
 
+RISC-V AIA DRIVERS
+M:	Anup Patel <anup@brainfault.org>
+L:	linux-riscv@lists.infradead.org
+S:	Maintained
+F:	Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
+F:	Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml
+F:	drivers/irqchip/irq-riscv-aplic-*.c
+F:	drivers/irqchip/irq-riscv-aplic-*.h
+F:	drivers/irqchip/irq-riscv-imsic-*.c
+F:	drivers/irqchip/irq-riscv-imsic-*.h
+F:	drivers/irqchip/irq-riscv-intc.c
+F:	include/linux/irqchip/riscv-aplic.h
+F:	include/linux/irqchip/riscv-imsic.h
+
 RISC-V ARCHITECTURE
 M:	Paul Walmsley <paul.walmsley@sifive.com>
 M:	Palmer Dabbelt <palmer@dabbelt.com>