From patchwork Tue Aug 1 11:58:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 129272 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:918b:0:b0:3e4:2afc:c1 with SMTP id s11csp2640894vqg; Tue, 1 Aug 2023 05:43:56 -0700 (PDT) X-Google-Smtp-Source: APBJJlHshYqTA9m3KxnAaggeioqT8MWOLQulMvMEsYQ4chovUeJcOzZYyyDIoAdGfGbl4ewWwICC X-Received: by 2002:aa7:c616:0:b0:522:2711:863 with SMTP id h22-20020aa7c616000000b0052227110863mr2684699edq.1.1690893836150; Tue, 01 Aug 2023 05:43:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690893836; cv=none; d=google.com; s=arc-20160816; b=Ff/Z/VQ6sDusFm3c5cExMpI7O++gDNHeFP2+0SThrmzr9EW7ytjAtfoCQtGbeHZTdl Qwhfw3E0rbNrW/qhZWRFheXN4yVimUvf2wcs+oYchlukYEFtsiqsCl/nLorXGChTcviU FFzIS3iqkx9xGtZAa8AE/yLilm5UnlPB0xFWcmrDs4bsIQb9c91SKJNrEiYoGYqfxqt5 bJmeVc4Ob0v3a+WVTyAeM0C866fEmesFJ3edJwlPvRH+UwcILSwVVOqL2m30U61nGBkv x2680p/82zIuveYoIFovWdxAdRoiioUVfMZteYF/tgVKUpdvEtpOOJJ6sunSKQD3u5IX ZKSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=o9Pu/IQwVvSKv7AS8sSkHsMqYz5XPVZGxLsslDDucN8=; fh=wVZEQimxp/UyE4Mf0Sn+nsZcfrBLHvkvU7kacOC/59o=; b=yHLiMXiRfwQRBiPa0OlTlYC9oKNyA2YBjA5IFAVNL1cAzw4+2j3tUQE/rtf7V+YeZo YEw0wQzpVeWOyhgtHFZ5aybM5isFdNlkxZ3T6okau5jPFBlV19Q60EoIY2yf+yn0zyz2 RHxzVczEpW4AqoP1AAZHyVOpJY/Jv/e2pOAa9eU6XtwElByxAjrJvBY4vfjvUIdD+ThU /jaI5o14fGVD21TJmhHbbVpPzG59ebclMHjXHnmo40uwx/CGCRAZQJSMhKKtbHktWio3 ZewPG/Bfr22vhbbXybHLyR+e/G3mVXXxt48mQwfNgUs10O7MR+CZwF7j4jlUaGXfGk3B 7rmA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=fG5q2AQX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ay2-20020a056402202200b00522b8ea875bsi4634773edb.278.2023.08.01.05.43.32; Tue, 01 Aug 2023 05:43:56 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=fG5q2AQX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234429AbjHAL71 (ORCPT + 99 others); Tue, 1 Aug 2023 07:59:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50354 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232022AbjHAL7I (ORCPT ); Tue, 1 Aug 2023 07:59:08 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 74EA31723 for ; Tue, 1 Aug 2023 04:59:07 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 93E5C6607190; Tue, 1 Aug 2023 12:59:05 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1690891146; bh=U7o24sdxWuUf0KSP3Kk3p2PcTD6H7BVTWeW9U4Sw7qo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fG5q2AQXBrxpVYXCYE+BbjudouUSaJ9P2NXDIvfFKsF3SIWSjXJAYX0avT3px5QXu r4nhdf8ps3nt2w2100yTvPO3eS9UEWviveoZr3w0Mmz8WaMXxnVQN35HpKrrRTcLkv zdX8eNM0JqN63NCR+726oTfZ+gSjn+MYAooB+Cof6o/oFNGUTy4JWXhraFntwIkoX6 1wCI9Zdmzr+lnQm1nB18vZtUsL7VpN4scd5ejaL7+l/sLibUpwx4NK/MHsSwIfxs5z zXiTCdAln9UEVtuKgE/N6uEtsocF+85uBb7q90uQyk4H/TYSs01PTmaadgtM7sVM7N +WY9A57j1nOVQ== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, "Jason-JH . Lin" , Alexandre Mergnat Subject: [PATCH v8 06/13] drm/mediatek: gamma: Use bitfield macros Date: Tue, 1 Aug 2023 13:58:47 +0200 Message-ID: <20230801115854.150346-7-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230801115854.150346-1-angelogioacchino.delregno@collabora.com> References: <20230801115854.150346-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773030694989154108 X-GMAIL-MSGID: 1773030694989154108 Make the code more robust and improve readability by using bitfield macros instead of open coding bit operations. While at it, also add a definition for LUT_BITS_DEFAULT. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 41 ++++++++++++++--------- 1 file changed, 26 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index b9dc8754187d..4f642fed432f 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -3,6 +3,7 @@ * Copyright (c) 2021 MediaTek Inc. */ +#include #include #include #include @@ -21,9 +22,16 @@ #define GAMMA_LUT_EN BIT(1) #define GAMMA_DITHERING BIT(2) #define DISP_GAMMA_SIZE 0x0030 +#define DISP_GAMMA_SIZE_HSIZE GENMASK(28, 16) +#define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) #define DISP_GAMMA_LUT 0x0700 +#define DISP_GAMMA_LUT_10BIT_R GENMASK(29, 20) +#define DISP_GAMMA_LUT_10BIT_G GENMASK(19, 10) +#define DISP_GAMMA_LUT_10BIT_B GENMASK(9, 0) + #define LUT_10BIT_MASK 0x03ff +#define LUT_BITS_DEFAULT 10 struct mtk_disp_gamma_data { bool has_dither; @@ -90,33 +98,33 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, for (i = 0; i < lut_size; i++) { struct drm_color_lut diff, hwlut; - hwlut.red = drm_color_lut_extract(lut[i].red, 10); - hwlut.green = drm_color_lut_extract(lut[i].green, 10); - hwlut.blue = drm_color_lut_extract(lut[i].blue, 10); + hwlut.red = drm_color_lut_extract(lut[i].red, LUT_BITS_DEFAULT); + hwlut.green = drm_color_lut_extract(lut[i].green, LUT_BITS_DEFAULT); + hwlut.blue = drm_color_lut_extract(lut[i].blue, LUT_BITS_DEFAULT); if (!lut_diff || (i % 2 == 0)) { - word = hwlut.red << 20 + - hwlut.green << 10 + - hwlut.red; + word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); } else { diff.red = lut[i].red - lut[i - 1].red; - diff.red = drm_color_lut_extract(diff.red, 10); + diff.red = drm_color_lut_extract(diff.red, LUT_BITS_DEFAULT); diff.green = lut[i].green - lut[i - 1].green; - diff.green = drm_color_lut_extract(diff.green, 10); + diff.green = drm_color_lut_extract(diff.green, LUT_BITS_DEFAULT); diff.blue = lut[i].blue - lut[i - 1].blue; - diff.blue = drm_color_lut_extract(diff.blue, 10); + diff.blue = drm_color_lut_extract(diff.blue, LUT_BITS_DEFAULT); - word = diff.blue << 20 + - diff.green << 10 + - diff.red; + word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); } writel(word, (lut_base + i * 4)); } /* Enable the gamma table */ - cfg_val = cfg_val | GAMMA_LUT_EN; + cfg_val |= FIELD_PREP(GAMMA_LUT_EN, 1); writel(cfg_val, regs + DISP_GAMMA_CFG); } @@ -133,9 +141,12 @@ void mtk_gamma_config(struct device *dev, unsigned int w, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); + u32 sz; + + sz = FIELD_PREP(DISP_GAMMA_SIZE_HSIZE, w); + sz |= FIELD_PREP(DISP_GAMMA_SIZE_VSIZE, h); - mtk_ddp_write(cmdq_pkt, h << 16 | w, &gamma->cmdq_reg, gamma->regs, - DISP_GAMMA_SIZE); + mtk_ddp_write(cmdq_pkt, sz, &gamma->cmdq_reg, gamma->regs, DISP_GAMMA_SIZE); if (gamma->data && gamma->data->has_dither) mtk_dither_set_common(gamma->regs, &gamma->cmdq_reg, bpc, DISP_GAMMA_CFG, GAMMA_DITHERING, cmdq_pkt);