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Lin" , Alexandre Mergnat Subject: [PATCH v7 11/13] drm/mediatek: gamma: Program gamma LUT type for descending or rising Date: Mon, 31 Jul 2023 15:04:39 +0200 Message-ID: <20230731130441.173960-12-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230731130441.173960-1-angelogioacchino.delregno@collabora.com> References: <20230731130441.173960-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772950091413278141 X-GMAIL-MSGID: 1772950091413278141 All of the SoCs that don't have dithering control in the gamma IP have got a GAMMA_LUT_TYPE bit that tells to the IP if the LUT is "descending" (bit set) or "rising" (bit cleared): make sure to set it correctly after programming the LUT. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 659d5c512238..6fa3f583f8a1 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -22,6 +22,7 @@ #define GAMMA_RELAY_MODE BIT(0) #define GAMMA_LUT_EN BIT(1) #define GAMMA_DITHERING BIT(2) +#define GAMMA_LUT_TYPE BIT(2) #define DISP_GAMMA_SIZE 0x0030 #define DISP_GAMMA_SIZE_HSIZE GENMASK(28, 16) #define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) @@ -86,6 +87,16 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev) return LUT_SIZE_DEFAULT; } +static bool mtk_gamma_lut_is_descending(struct drm_color_lut *lut, u32 lut_size) +{ + u64 first, last; + + first = lut[0].red + lut[0].green + lut[0].blue; + last = lut[lut_size].red + lut[lut_size].green + lut[lut_size].blue; + + return !!(first > last); +} + /* * SoCs supporting 12-bits LUTs are using a new register layout that does * always support (by HW) both 12-bits and 10-bits LUT but, on those, we @@ -193,6 +204,14 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt } } + if (gamma && gamma->data && !gamma->data->has_dither) { + /* Descending or Rising LUT */ + if (mtk_gamma_lut_is_descending(lut, lut_size)) + cfg_val |= FIELD_PREP(GAMMA_LUT_TYPE, 1); + else + cfg_val &= ~GAMMA_LUT_TYPE; + } + /* Enable the gamma table */ cfg_val |= FIELD_PREP(GAMMA_LUT_EN, 1);