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[83.9.32.15]) by smtp.gmail.com with ESMTPSA id m8-20020a2e97c8000000b002b6fed37b18sm580048ljj.101.2023.08.04.13.09.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Aug 2023 13:09:17 -0700 (PDT) From: Konrad Dybcio Date: Fri, 04 Aug 2023 22:09:10 +0200 Subject: [PATCH 3/6] media: venus: hfi_venus: Support only updating certain bits with presets MIME-Version: 1.0 Message-Id: <20230731-topic-8280_venus-v1-3-8c8bbe1983a5@linaro.org> References: <20230731-topic-8280_venus-v1-0-8c8bbe1983a5@linaro.org> In-Reply-To: <20230731-topic-8280_venus-v1-0-8c8bbe1983a5@linaro.org> To: Stanimir Varbanov , Vikash Garodia , Bryan O'Donoghue , Andy Gross , Bjorn Andersson , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , Konrad Dybcio , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1691179750; l=1766; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=rfPsf8y53fs4Evjoavn1JhvaL4tSt9nvOlejrwjRPcs=; b=U/fipOBf+0qivdKHsXRSvN7IhCjwjrfmB7mycj+31aGgBfUSrWLGMzJyNLijmanSnHRoOwQzv bIS5lH6TZ1HDp1/nBGo8nrfgDQpSpjhDtDr4hGnOtsTyrUXwx23AYvz X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1773335516713006309 X-GMAIL-MSGID: 1773340158265612120 On some platforms (like SM8350) we're expected to only touch certain bits (such as 0 and 4 corresponding to mask 0x11). Add support for doing so. Signed-off-by: Konrad Dybcio --- drivers/media/platform/qcom/venus/core.h | 1 + drivers/media/platform/qcom/venus/hfi_venus.c | 15 ++++++++++++--- 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/qcom/venus/core.h b/drivers/media/platform/qcom/venus/core.h index d996abd339e1..2999c24392f5 100644 --- a/drivers/media/platform/qcom/venus/core.h +++ b/drivers/media/platform/qcom/venus/core.h @@ -38,6 +38,7 @@ struct freq_tbl { struct reg_val { u32 reg; u32 value; + u32 mask; }; struct bw_tbl { diff --git a/drivers/media/platform/qcom/venus/hfi_venus.c b/drivers/media/platform/qcom/venus/hfi_venus.c index 19fc6575a489..d4bad66f7293 100644 --- a/drivers/media/platform/qcom/venus/hfi_venus.c +++ b/drivers/media/platform/qcom/venus/hfi_venus.c @@ -349,10 +349,19 @@ static void venus_set_registers(struct venus_hfi_device *hdev) const struct venus_resources *res = hdev->core->res; const struct reg_val *tbl = res->reg_tbl; unsigned int count = res->reg_tbl_size; - unsigned int i; + unsigned int i, val; + + for (i = 0; i < count; i++) { + val = tbl[i].value; - for (i = 0; i < count; i++) - writel(tbl[i].value, hdev->core->base + tbl[i].reg); + /* In some cases, we only want to update certain bits */ + if (tbl[i].mask) { + val = readl(hdev->core->base + tbl[i].reg); + val = (val & ~tbl[i].mask) | (tbl[i].value & tbl[i].mask); + } + + writel(val, hdev->core->base + tbl[i].reg); + } } static void venus_soft_int(struct venus_hfi_device *hdev)