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[2620:137:e000::1:20]) by mx.google.com with ESMTP id z33-20020a056a001da100b006870878c6dbsi592155pfw.191.2023.07.27.15.59.21; Thu, 27 Jul 2023 15:59:34 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@me.com header.s=1a1hai header.b="d/MlOAXS"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=me.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232503AbjG0Vwm (ORCPT + 99 others); Thu, 27 Jul 2023 17:52:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232460AbjG0Vwh (ORCPT ); Thu, 27 Jul 2023 17:52:37 -0400 Received: from qs51p00im-qukt01072702.me.com (qs51p00im-qukt01072702.me.com [17.57.155.17]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F21BF2D7D for ; Thu, 27 Jul 2023 14:52:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=me.com; s=1a1hai; t=1690494752; bh=EKT0P4uKrlnLCWiETQ0sfCoQQG3MVyK9PAIfabQ3Emk=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=d/MlOAXS/mEyU3KCJwIW33yeUvH+eZuVBK2BS5PL9BSyLuQ12XTllK9CghVqlBTlp Q0VvyFFfoTCgE1W35W7HZVNDORG3ZtOKnZWj7gadC9RtUHaKYvY8tPrUOewIIJNabK XSjxXnnpsfIAcn0u45WKcJNjgFMrN4S1rd1c3WG6zgm6b1kpvd5TGlHNZN2bVfuYQX s0LbGQwsMfKbK+RMlPhVwbi4W5Zdhzgo1RI5kTN3R3JlvmUZnGzfG6QS1/+3I95qfx zgpiBqauUHy9l+egeTqnGtJjKdIHv68WzhhdcgedaJOIrlzgsOS8WqR2Mi8tiO7886 QAl2LYw912jLA== Received: from localhost (qs51p00im-dlb-asmtp-mailmevip.me.com [17.57.155.28]) by qs51p00im-qukt01072702.me.com (Postfix) with ESMTPSA id 79C2A168029B; Thu, 27 Jul 2023 21:52:31 +0000 (UTC) From: Alain Volmat To: Alain Volmat , David Airlie , Daniel Vetter Cc: Alain Volmat , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 04/14] drm/sti: add STih418 platform support in sti mixer Date: Thu, 27 Jul 2023 21:51:28 +0000 Message-Id: <20230727215141.53910-5-avolmat@me.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230727215141.53910-1-avolmat@me.com> References: <20230727215141.53910-1-avolmat@me.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: PvSYlyyofV4n7uFJ2g7UV5nGOgilZbu_ X-Proofpoint-GUID: PvSYlyyofV4n7uFJ2g7UV5nGOgilZbu_ X-Proofpoint-Virus-Version: =?utf-8?q?vendor=3Dfsecure_engine=3D1=2E1=2E170-?= =?utf-8?q?22c6f66c430a71ce266a39bfe25bc2903e8d5c8f=3A6=2E0=2E138=2C18=2E0?= =?utf-8?q?=2E790=2C17=2E11=2E62=2E513=2E0000000_definitions=3D2022-01-12=5F?= =?utf-8?q?02=3A2020-02-14=5F02=2C2022-01-12=5F02=2C2021-12-02=5F01_signatur?= =?utf-8?q?es=3D0?= X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 phishscore=0 mlxscore=0 spamscore=0 suspectscore=0 malwarescore=0 bulkscore=0 clxscore=1015 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2307270199 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772616442870048505 X-GMAIL-MSGID: 1772616442870048505 On the STiH418, since there are more planes attached to the mixer, the bit field for each depth of is now coded using 4 bits instead of 3 bits. Some registers as well differ between STiH407 and STiH418 leading on relying on the st,stih418-compositor compatible to distinguish proper behavior. Signed-off-by: Alain Volmat --- drivers/gpu/drm/sti/sti_mixer.c | 71 ++++++++++++++++++++++++++------- 1 file changed, 57 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/sti/sti_mixer.c b/drivers/gpu/drm/sti/sti_mixer.c index 7e5f14646625..9cd780403d7b 100644 --- a/drivers/gpu/drm/sti/sti_mixer.c +++ b/drivers/gpu/drm/sti/sti_mixer.c @@ -7,6 +7,7 @@ */ #include +#include #include #include @@ -23,10 +24,12 @@ module_param_named(bkgcolor, bkg_color, int, 0644); /* regs offset */ #define GAM_MIXER_CTL 0x00 #define GAM_MIXER_BKC 0x04 +#define GAM_MIXER_OFF 0x08 /* Only for STiH418 */ #define GAM_MIXER_BCO 0x0C #define GAM_MIXER_BCS 0x10 #define GAM_MIXER_AVO 0x28 #define GAM_MIXER_AVS 0x2C +#define GAM_MIXER_CRB2 0x30 /* Only for STiH418 */ #define GAM_MIXER_CRB 0x34 #define GAM_MIXER_ACT 0x38 #define GAM_MIXER_MBP 0x3C @@ -102,13 +105,22 @@ static void mixer_dbg_ctl(struct seq_file *s, int val) seq_puts(s, "Nothing"); } -static void mixer_dbg_crb(struct seq_file *s, int val) +static void mixer_dbg_crb(struct seq_file *s, struct sti_mixer *mixer, u64 val) { int i; + u32 shift, mask_id; + + if (of_device_is_compatible(mixer->dev->of_node, "st,stih418-compositor")) { + shift = 4; + mask_id = 0x0f; + } else { + shift = 3; + mask_id = 0x07; + } seq_puts(s, "\tDepth: "); for (i = 0; i < GAM_MIXER_NB_DEPTH_LEVEL; i++) { - switch (val & GAM_DEPTH_MASK_ID) { + switch (val & mask_id) { case GAM_DEPTH_VID0_ID: seq_puts(s, "VID0"); break; @@ -133,7 +145,7 @@ static void mixer_dbg_crb(struct seq_file *s, int val) if (i < GAM_MIXER_NB_DEPTH_LEVEL - 1) seq_puts(s, " < "); - val = val >> 3; + val = val >> shift; } } @@ -149,6 +161,7 @@ static int mixer_dbg_show(struct seq_file *s, void *arg) { struct drm_info_node *node = s->private; struct sti_mixer *mixer = (struct sti_mixer *)node->info_ent->data; + u64 val; seq_printf(s, "%s: (vaddr = 0x%p)", sti_mixer_to_str(mixer), mixer->regs); @@ -161,11 +174,18 @@ static int mixer_dbg_show(struct seq_file *s, void *arg) DBGFS_DUMP(GAM_MIXER_AVO); DBGFS_DUMP(GAM_MIXER_AVS); DBGFS_DUMP(GAM_MIXER_CRB); - mixer_dbg_crb(s, sti_mixer_reg_read(mixer, GAM_MIXER_CRB)); + val = sti_mixer_reg_read(mixer, GAM_MIXER_CRB); + if (of_device_is_compatible(mixer->dev->of_node, "st,stih418-compositor")) { + DBGFS_DUMP(GAM_MIXER_CRB2); + val |= ((u64)sti_mixer_reg_read(mixer, GAM_MIXER_CRB2) << 32); + } + mixer_dbg_crb(s, mixer, val); DBGFS_DUMP(GAM_MIXER_ACT); - DBGFS_DUMP(GAM_MIXER_MBP); - DBGFS_DUMP(GAM_MIXER_MX0); - mixer_dbg_mxn(s, mixer->regs + GAM_MIXER_MX0); + if (of_device_is_compatible(mixer->dev->of_node, "st,stih407-compositor")) { + DBGFS_DUMP(GAM_MIXER_MBP); + DBGFS_DUMP(GAM_MIXER_MX0); + mixer_dbg_mxn(s, mixer->regs + GAM_MIXER_MX0); + } seq_putc(s, '\n'); return 0; } @@ -238,7 +258,16 @@ int sti_mixer_set_plane_depth(struct sti_mixer *mixer, struct sti_plane *plane) { int plane_id, depth = plane->drm_plane.state->normalized_zpos; unsigned int i; - u32 mask, val; + u64 mask, val; + u32 shift, mask_id; + + if (of_device_is_compatible(mixer->dev->of_node, "st,stih418-compositor")) { + shift = 4; + mask_id = 0x0f; + } else { + shift = 3; + mask_id = 0x07; + } switch (plane->desc) { case STI_GDP_0: @@ -266,26 +295,37 @@ int sti_mixer_set_plane_depth(struct sti_mixer *mixer, struct sti_plane *plane) /* Search if a previous depth was already assigned to the plane */ val = sti_mixer_reg_read(mixer, GAM_MIXER_CRB); + if (of_device_is_compatible(mixer->dev->of_node, "st,stih418-compositor")) + val |= ((u64)sti_mixer_reg_read(mixer, GAM_MIXER_CRB2) << 32); for (i = 0; i < GAM_MIXER_NB_DEPTH_LEVEL; i++) { - mask = GAM_DEPTH_MASK_ID << (3 * i); - if ((val & mask) == plane_id << (3 * i)) + mask = mask_id << (shift * i); + if ((val & mask) == plane_id << (shift * i)) break; } - mask |= GAM_DEPTH_MASK_ID << (3 * depth); - plane_id = plane_id << (3 * depth); + mask |= mask_id << (shift * depth); + plane_id = plane_id << (shift * depth); DRM_DEBUG_DRIVER("%s %s depth=%d\n", sti_mixer_to_str(mixer), sti_plane_to_str(plane), depth); dev_dbg(mixer->dev, "GAM_MIXER_CRB val 0x%x mask 0x%x\n", - plane_id, mask); + plane_id, (u32)(mask & 0xffffffff)); + if (of_device_is_compatible(mixer->dev->of_node, "st,stih418-compositor")) + dev_dbg(mixer->dev, "GAM_MIXER_CRB2 val 0x%x mask 0x%x\n", + plane_id, (u32)(mask >> 32)); val &= ~mask; val |= plane_id; - sti_mixer_reg_write(mixer, GAM_MIXER_CRB, val); + sti_mixer_reg_write(mixer, GAM_MIXER_CRB, val & 0xffffffff); + if (of_device_is_compatible(mixer->dev->of_node, "st,stih418-compositor")) + sti_mixer_reg_write(mixer, GAM_MIXER_CRB2, val >> 32); dev_dbg(mixer->dev, "Read GAM_MIXER_CRB 0x%x\n", sti_mixer_reg_read(mixer, GAM_MIXER_CRB)); + if (of_device_is_compatible(mixer->dev->of_node, "st,stih418-compositor")) + dev_dbg(mixer->dev, "Read GAM_MIXER_CRB2 0x%x\n", + sti_mixer_reg_read(mixer, GAM_MIXER_CRB2)); + return 0; } @@ -352,6 +392,9 @@ int sti_mixer_set_plane_status(struct sti_mixer *mixer, val |= status ? mask : 0; sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val); + if (of_device_is_compatible(mixer->dev->of_node, "st,stih418-compositor")) + sti_mixer_reg_write(mixer, GAM_MIXER_OFF, 0x02); + return 0; }