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And in any case, this helps us get away from infering the generation from the numerical chip-id. v2: Fix is_a2xx() typo Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/adreno_device.c | 31 ++++++++++++++- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 11 +++--- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 46 ++++++++++++++++------ 3 files changed, 70 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 325b25dc8bfd..e014d85a60cc 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -23,6 +23,7 @@ module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600); static const struct adreno_info gpulist[] = { { .rev = ADRENO_REV(2, 0, 0, 0), + .family = ADRENO_2XX_GEN1, .revn = 200, .fw = { [ADRENO_FW_PM4] = "yamato_pm4.fw", @@ -33,6 +34,7 @@ static const struct adreno_info gpulist[] = { .init = a2xx_gpu_init, }, { /* a200 on i.mx51 has only 128kib gmem */ .rev = ADRENO_REV(2, 0, 0, 1), + .family = ADRENO_2XX_GEN1, .revn = 201, .fw = { [ADRENO_FW_PM4] = "yamato_pm4.fw", @@ -43,6 +45,7 @@ static const struct adreno_info gpulist[] = { .init = a2xx_gpu_init, }, { .rev = ADRENO_REV(2, 2, 0, ANY_ID), + .family = ADRENO_2XX_GEN2, .revn = 220, .fw = { [ADRENO_FW_PM4] = "leia_pm4_470.fw", @@ -53,6 +56,7 @@ static const struct adreno_info gpulist[] = { .init = a2xx_gpu_init, }, { .rev = ADRENO_REV(3, 0, 5, ANY_ID), + .family = ADRENO_3XX, .revn = 305, .fw = { [ADRENO_FW_PM4] = "a300_pm4.fw", @@ -63,6 +67,7 @@ static const struct adreno_info gpulist[] = { .init = a3xx_gpu_init, }, { .rev = ADRENO_REV(3, 0, 6, 0), + .family = ADRENO_3XX, .revn = 307, /* because a305c is revn==306 */ .fw = { [ADRENO_FW_PM4] = "a300_pm4.fw", @@ -73,6 +78,7 @@ static const struct adreno_info gpulist[] = { .init = a3xx_gpu_init, }, { .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID), + .family = ADRENO_3XX, .revn = 320, .fw = { [ADRENO_FW_PM4] = "a300_pm4.fw", @@ -83,6 +89,7 @@ static const struct adreno_info gpulist[] = { .init = a3xx_gpu_init, }, { .rev = ADRENO_REV(3, 3, 0, ANY_ID), + .family = ADRENO_3XX, .revn = 330, .fw = { [ADRENO_FW_PM4] = "a330_pm4.fw", @@ -93,6 +100,7 @@ static const struct adreno_info gpulist[] = { .init = a3xx_gpu_init, }, { .rev = ADRENO_REV(4, 0, 5, ANY_ID), + .family = ADRENO_4XX, .revn = 405, .fw = { [ADRENO_FW_PM4] = "a420_pm4.fw", @@ -103,6 +111,7 @@ static const struct adreno_info gpulist[] = { .init = a4xx_gpu_init, }, { .rev = ADRENO_REV(4, 2, 0, ANY_ID), + .family = ADRENO_4XX, .revn = 420, .fw = { [ADRENO_FW_PM4] = "a420_pm4.fw", @@ -113,6 +122,7 @@ static const struct adreno_info gpulist[] = { .init = a4xx_gpu_init, }, { .rev = ADRENO_REV(4, 3, 0, ANY_ID), + .family = ADRENO_4XX, .revn = 430, .fw = { [ADRENO_FW_PM4] = "a420_pm4.fw", @@ -123,6 +133,7 @@ static const struct adreno_info gpulist[] = { .init = a4xx_gpu_init, }, { .rev = ADRENO_REV(5, 0, 6, ANY_ID), + .family = ADRENO_5XX, .revn = 506, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", @@ -140,6 +151,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a506_zap.mdt", }, { .rev = ADRENO_REV(5, 0, 8, ANY_ID), + .family = ADRENO_5XX, .revn = 508, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", @@ -156,6 +168,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a508_zap.mdt", }, { .rev = ADRENO_REV(5, 0, 9, ANY_ID), + .family = ADRENO_5XX, .revn = 509, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", @@ -173,6 +186,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a512_zap.mdt", }, { .rev = ADRENO_REV(5, 1, 0, ANY_ID), + .family = ADRENO_5XX, .revn = 510, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", @@ -187,6 +201,7 @@ static const struct adreno_info gpulist[] = { .init = a5xx_gpu_init, }, { .rev = ADRENO_REV(5, 1, 2, ANY_ID), + .family = ADRENO_5XX, .revn = 512, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", @@ -203,6 +218,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a512_zap.mdt", }, { .rev = ADRENO_REV(5, 3, 0, 2), + .family = ADRENO_5XX, .revn = 530, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", @@ -221,6 +237,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a530_zap.mdt", }, { .rev = ADRENO_REV(5, 4, 0, ANY_ID), + .family = ADRENO_5XX, .revn = 540, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", @@ -238,6 +255,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a540_zap.mdt", }, { .rev = ADRENO_REV(6, 1, 0, ANY_ID), + .family = ADRENO_6XX_GEN1, .revn = 610, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", @@ -263,6 +281,7 @@ static const struct adreno_info gpulist[] = { ), }, { .rev = ADRENO_REV(6, 1, 8, ANY_ID), + .family = ADRENO_6XX_GEN1, .revn = 618, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", @@ -280,6 +299,7 @@ static const struct adreno_info gpulist[] = { }, { .machine = "qcom,sm4350", .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .family = ADRENO_6XX_GEN1, .revn = 619, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", @@ -298,6 +318,7 @@ static const struct adreno_info gpulist[] = { }, { .machine = "qcom,sm6375", .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .family = ADRENO_6XX_GEN1, .revn = 619, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", @@ -315,6 +336,7 @@ static const struct adreno_info gpulist[] = { ), }, { .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .family = ADRENO_6XX_GEN1, .revn = 619, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", @@ -335,6 +357,7 @@ static const struct adreno_info gpulist[] = { ), }, { .rev = ADRENO_REV(6, 3, 0, ANY_ID), + .family = ADRENO_6XX_GEN1, .revn = 630, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", @@ -348,6 +371,7 @@ static const struct adreno_info gpulist[] = { .hwcg = a630_hwcg, }, { .rev = ADRENO_REV(6, 4, 0, ANY_ID), + .family = ADRENO_6XX_GEN2, .revn = 640, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", @@ -365,6 +389,7 @@ static const struct adreno_info gpulist[] = { ), }, { .rev = ADRENO_REV(6, 5, 0, ANY_ID), + .family = ADRENO_6XX_GEN3, .revn = 650, .fw = { [ADRENO_FW_SQE] = "a650_sqe.fw", @@ -386,6 +411,7 @@ static const struct adreno_info gpulist[] = { ), }, { .rev = ADRENO_REV(6, 6, 0, ANY_ID), + .family = ADRENO_6XX_GEN4, .revn = 660, .fw = { [ADRENO_FW_SQE] = "a660_sqe.fw", @@ -401,6 +427,7 @@ static const struct adreno_info gpulist[] = { .address_space_size = SZ_16G, }, { .rev = ADRENO_REV(6, 3, 5, ANY_ID), + .family = ADRENO_6XX_GEN4, .fw = { [ADRENO_FW_SQE] = "a660_sqe.fw", [ADRENO_FW_GMU] = "a660_gmu.bin", @@ -419,6 +446,7 @@ static const struct adreno_info gpulist[] = { ), }, { .rev = ADRENO_REV(6, 8, 0, ANY_ID), + .family = ADRENO_6XX_GEN2, .revn = 680, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", @@ -432,6 +460,7 @@ static const struct adreno_info gpulist[] = { .hwcg = a640_hwcg, }, { .rev = ADRENO_REV(6, 9, 0, ANY_ID), + .family = ADRENO_6XX_GEN4, .fw = { [ADRENO_FW_SQE] = "a660_sqe.fw", [ADRENO_FW_GMU] = "a690_gmu.bin", @@ -641,7 +670,7 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major, config.rev.minor, config.rev.patchid); - priv->is_a2xx = config.rev.core == 2; + priv->is_a2xx = info->family < ADRENO_3XX; priv->has_cached_coherent = !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index f4d45534dd7f..1951036b2308 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -1080,8 +1080,13 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, u32 speedbin; int ret; + adreno_gpu->funcs = funcs; + adreno_gpu->info = adreno_info(config->rev); + adreno_gpu->rev = *rev; + /* Only handle the core clock when GMU is not in use (or is absent). */ - if (adreno_has_gmu_wrapper(adreno_gpu) || config->rev.core < 6) { + if (adreno_has_gmu_wrapper(adreno_gpu) || + adreno_gpu->info->family < ADRENO_6XX_GEN1) { /* * This can only be done before devm_pm_opp_of_add_table(), or * dev_pm_opp_set_config() will WARN_ON() @@ -1097,10 +1102,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, devm_pm_opp_set_clkname(dev, "core"); } - adreno_gpu->funcs = funcs; - adreno_gpu->info = adreno_info(config->rev); - adreno_gpu->rev = *rev; - if (adreno_read_speedbin(dev, &speedbin) || !speedbin) speedbin = 0xffff; adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index fe7afac5b059..14af16080bd0 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -29,6 +29,25 @@ enum { ADRENO_FW_MAX, }; +/** + * @enum adreno_family: identify generation and possibly sub-generation + * + * In some cases there are distinct sub-generations within a major revision + * so it helps to be able to group the GPU devices by generation and if + * necessary sub-generation. + */ +enum adreno_family { + ADRENO_2XX_GEN1, /* a20x */ + ADRENO_2XX_GEN2, /* a22x */ + ADRENO_3XX, + ADRENO_4XX, + ADRENO_5XX, + ADRENO_6XX_GEN1, /* a630 family */ + ADRENO_6XX_GEN2, /* a640 family */ + ADRENO_6XX_GEN3, /* a650 family */ + ADRENO_6XX_GEN4, /* a660 family */ +}; + #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0) #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1) #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) @@ -68,6 +87,7 @@ struct adreno_speedbin { struct adreno_info { const char *machine; struct adreno_rev rev; + enum adreno_family family; uint32_t revn; const char *fw[ADRENO_FW_MAX]; uint32_t gmem; @@ -193,14 +213,14 @@ static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu) { if (WARN_ON_ONCE(!gpu->info)) return false; - return (gpu->info->revn < 300); + return gpu->info->family <= ADRENO_2XX_GEN2; } static inline bool adreno_is_a20x(const struct adreno_gpu *gpu) { if (WARN_ON_ONCE(!gpu->info)) return false; - return (gpu->info->revn < 210); + return gpu->info->family == ADRENO_2XX_GEN1; } static inline bool adreno_is_a225(const struct adreno_gpu *gpu) @@ -343,29 +363,31 @@ static inline int adreno_is_a690(const struct adreno_gpu *gpu) /* check for a615, a616, a618, a619 or any a630 derivatives */ static inline int adreno_is_a630_family(const struct adreno_gpu *gpu) { - return adreno_is_revn(gpu, 630) || - adreno_is_revn(gpu, 615) || - adreno_is_revn(gpu, 616) || - adreno_is_revn(gpu, 618) || - adreno_is_revn(gpu, 619); + if (WARN_ON_ONCE(!gpu->info)) + return false; + return gpu->info->family == ADRENO_6XX_GEN1; } static inline int adreno_is_a660_family(const struct adreno_gpu *gpu) { - return adreno_is_a660(gpu) || adreno_is_a690(gpu) || adreno_is_7c3(gpu); + if (WARN_ON_ONCE(!gpu->info)) + return false; + return gpu->info->family == ADRENO_6XX_GEN4; } /* check for a650, a660, or any derivatives */ static inline int adreno_is_a650_family(const struct adreno_gpu *gpu) { - return adreno_is_revn(gpu, 650) || - adreno_is_revn(gpu, 620) || - adreno_is_a660_family(gpu); + if (WARN_ON_ONCE(!gpu->info)) + return false; + return gpu->info->family >= ADRENO_6XX_GEN3; } static inline int adreno_is_a640_family(const struct adreno_gpu *gpu) { - return adreno_is_a640(gpu) || adreno_is_a680(gpu); + if (WARN_ON_ONCE(!gpu->info)) + return false; + return gpu->info->family == ADRENO_6XX_GEN2; } u64 adreno_private_address_space_size(struct msm_gpu *gpu);